Data Center Power & Limits Architect

The Data Center Power & Limits Architect will define and drive next-generation power management, thermal, and system limits architecture for large-scale compute platforms (SOC, servers, racks, and cluster-level deployments).

With AI/HPC workloads pushing infrastructure to electrical and thermal limits, this role is responsible for enabling maximum sustained performance within constrained power, cooling, and reliability envelopes by architecting end-to-end power and limits systems across silicon, platform, and data center infrastructure.

Key Responsibilities

1. Power & Limits Architecture Definition

• Define holistic power, thermal, and electrical limits architecture across silicon, board, system, rack, and cluster levels
• Architect power budgeting, allocation, and enforcement mechanisms across CPU, GPU, memory, accelerators, and I/O
• Develop strategies to maximize performance under datacenter-level constraints (rack power caps, cooling limits, PUE targets)

1. Dynamic Control & Optimization

• Architect advanced dynamic power control systems (e.g., DVFS/DCVS, AVS-like systems) for fast transient response
• Design closed-loop control systems using telemetry and feedback to optimize performance vs. constraints
• Develop proactive and reactive limit management (thermal throttling, power capping, workload shaping)

1. Telemetry & System Integration

• Define requirements and interfaces for telemetry infrastructure (sensors, BMC, firmware, system SW)
• Enable real-time monitoring and decision making across system layers
• Ensure integration with platform controllers (e.g., BMC/EC, rack management, orchestration layers)

1. Cross-Layer Co-Design

• Collaborate with:
• Silicon/SoC architects (power islands, regulators, sensors)
• Platform teams (VRs, PDN, cooling)
• Software/firmware teams (power management algorithms)
• Data center infrastructure teams (rack-level optimization)
• Define hardware/software partitioning for limits enforcement with minimal overhead

1. Modeling, Simulation & Validation

• Develop system-level models (MATLAB/Simulink, architectural simulators) to:
• Predict performance vs. power/thermal constraints
• Evaluate algorithms and architecture trade-offs
• Perform workload-driven analysis to validate architecture decisions

1. Innovation & Future Architecture

• Drive innovations in:
• Power delivery efficiency
• Thermal-aware scheduling
• AI workload-aware limits
• Rack/cluster-level power orchestration
• Define next-generation architectures to support scaling AI/HPC performance under constrained infrastructure, To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

Network Operations Center, Computer Systems, Network Operations Center, Power Management, System Architecture, Power Generation, Thermal Management, Artificial Intelligence (AI), Electricity, Multiplatform/Cross-Platform, * 10+ years of experience in power architecture, system architecture, or related domains

• Deep expertise in:
• Power management systems and limits control
• Thermal and electrical constraints in high-performance systems
• DVFS/DCVS, power capping, and control systems
• Strong understanding of:
• Data center/server architecture (CPU/GPU/accelerators, memory systems)
• Power delivery networks (VRs, PDN, rack power distribution)
• Telemetry, sensors, and system monitoring
• Experience with modeling and analysis tools (e.g., MATLAB, Python), * Bachelor’’s degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience., Master’’s degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience., PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits:

$164,000.00 - $246,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.

Qualcomm Technologies, Inc.