Technical Lead, Front-End Power Optimization

The Technical Lead, Power Analysis andOptimization, is responsible for driving power efficiency from the microarchitecture level through to physical implementation. You will bridge the gap between RTL design and silicon power, ensuring our designs meet aggressive Power, Performance, and Area (PPA) targets. This role spans all phases of the front-end design cycle, combining deep technical expertise in power modeling with leadership in cross-functional coordination., * Evaluate ultra-high-bandwidth packet switching microarchitecture through a first-principles approach.

• Map application-level network traffic patterns to microarchitectural structures to pinpoint power inefficiencies.
• Develop a comprehensive understanding of the relationship between RTL design choices and their downstream impact on silicon power.
• Evolve beyond standard clock gating by implementing RTL modifications informed by application-specific traffic flow analysis.
• Integrate physical-aware methodologies early in the design cycle to ensure RTL architecture is inherently aligned with physical implementation constraints.
• Develop comprehensive power vectors that accurately simulate production-level network switching workloads.
• Utilize power vectors to perform precise power analysis, focusing on optimizations, IR drop, and droop profiling to identify and mitigate high-activity switching regions.
• Partner with the Physical Design (PD) team to understand c lock tree structure as well as other i mplementation choices and propose RTL enhancements accordingly .
• Facilitate structured reviews to confirm that proposed RTL enhancements remain physically viable and functionally verified.
• Conduct rigorous post-implementation analysis to verify that all physical optimizations successfully meet defined power targets.

• Bachelor’s Degree in Electrical or ComputerEngineering with 8+ years of experience or Master’s Degree in Electrical or Computer Engineering with 6+ years of experience, PhD in Electrical or Computer Engineering with 3+ years of experience.
• Experience in RTL design, optimization, and power modeling.
• Experience performingpower analysis using PrimePower RTL., * Experience in mapping application-level workloads to microarchitectural features to achieve measurable power reduction through RTL-level modifications.
• Experience in high-speed packet switching architectures.
• Experience with advanced FinFET process nodes (5nm, 3nm, or below).
• Experience with Tcl/Python scripting for automating power analysis and RTL optimization workflows.
• Experience to work across design, physical design and other power teams to solve complex power/performance challenges.
• Experience leading technical initiatives and facilitating cross-functional collaboration between design, physical design, and power analysis teams to meet PPA targets.

$183,800.00 to $263,600.00 life insurance, vision insurance, parental leave, paid holidays, sick time, 401(k), Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate’s hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours ofunused sick timecarried forwardfrom one calendar yearto the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

• .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
• 1.5% of incentive target for each 1% of attainment between 50% and 75%;
• 1% of incentive target for each 1% of attainment between 75% and 100%; and
• Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area: $183,800.00 - $303,100.00

Non-Metro New York state & Washington state: $163,600.00 - $269,800.00

• For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms like Silicon One are shaping the technology industry. We’re a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development from design to qualification to production is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world., Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.