Senior Engineer, AI/ML and Infrastructure

Samsung
Austin, TX, United States
2 months ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Experience required
2 years minimum
Compensation
$124,000.0 - $208,400.0
Working hours
Regular working hours
Job source

Tech stack

Java (Programming Language) Computer-Aided Design Agile Methodology Artificial Intelligence Data Analysis C++ (Programming Language) Computer Programming Computer Engineering Software Debugging DevOps Programming Tools Python (Programming Language)
+12 more
Machine Learning Software Engineering Systems Architecture Application Specific Integrated Circuits Generative AI Information Technology Power Analysis (Cryptography) Data Analytics Code Inspection Mentor Graphics Physical Design Programming Languages

Job description

As a GPU Design Technology Infrastructure Engineer, you will contribute to the development of scalable infrastructure and automation solutions that enable Samsung’s next-generation GPU and system-level IP development.

In this individual contributor role, you will support infrastructure, orchestration, and data-driven engineering solutions that enable design and CAD teams to execute complex workflows more efficiently. You will collaborate closely with software, CAD, IT, and advanced design technology teams to improve compute utilization, workflow automation, and AI/ML-driven engineering capabilities that enhance engineering productivity across the design development pipeline.

  • Contribute to development of scalable infrastructure and workflow orchestration solutions that improve engineering productivity and enable efficient execution of design and CAD workflows across multi-site development environments.
  • Support automation and data analysis initiatives that improve compute, storage, and licensing utilization while enabling broader access to engineering data and workflow insights across design technology teams.
  • Help develop modern, vendor-agnostic debug, analysis, and execution capabilities that improve visibility into design processes and support future AI/ML and Generative AI-driven engineering solutions.
  • Collaborate with CAD, IT, and advanced design technology teams to support methodology improvements across ASIC design flows, including RTL, verification, synthesis, physical design, timing, and power analysis workflows
  • Contribute to AI/ML-driven engineering initiatives and support legacy infrastructure solutions to improve workflow automation, scalability, and optimization efficiency across GPU and system-level IP development.

Requirements

  • 2+ years of experience with a Bachelor’s Degree in Computer Science, Computer Engineering, or relevant field, or completion of a Master’s Degree or Ph.D.
  • Experience in software development, physical design, system architecture, or related engineering domain with a focus on scalability, automation, and process improvement
  • Good programming skills in Python, C++, Java, or similar programming language
  • Familiarity with software development methodologies such as Agile or DevOps and experience with modern development tools and workflows
  • Working knowledge of low-power tools and methodologies, including RTL and gate-level power analysis, optimization, and signoff flows (e.g., PrimePower, PowerArtist, Empower, Joules, RTL-Architect, or equivalent)
  • Understanding of end-to-end ASIC design flows, including RTL, verification, synthesis, physical design, timing, power, and DTCO concepts
  • Familiarity with industry-standard CAD tools for simulation, synthesis, linting, and verification (e.g., Synopsys, Cadence, Mentor Graphics)
  • Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach.
  • Excellent collaboration and communication skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global environment., This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Benefits & conditions

At Samsung - SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $124,000 - $208,400. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.

Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.

Additionally, this role might be eligible to participate in long term incentive plan and relocation.

This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).

About the company

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!, The Advanced Design Technology and Design Implementation teams play a critical role in enabling GPU and system-level development within Samsung SARC/ACL and the broader System LSI organization. Operating at the intersection of design technology and physical implementation, we partner closely with Foundry from early technology exploration through the full development cycle. Spanning advanced design methodologies, GPU physical design, CAD, and DTCO, we accelerate adoption of leading technology nodes and deliver optimized power, performance, area (PPA), silicon quality, and turnaround time for next-generation IP solutions.

You will join a highly collaborative, fast-paced environment working across parallel development cycles with direct impact on consumer technologies used worldwide. Here, you’ll help build what’s next: experimenting with new ideas, broadening your technical expertise, and solving impactful challenges alongside talented teammates who value ownership, continuous learning, and growth.

Apply for this position

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