SW Engineer

Great opportunity to join Pre-Ipo creating the standard in Programmable IP for the communications infrastructure!

Ideal candidate will be responsible for development of synthesis libraries for use in ASIC design environment. Initial requirement will be to develop Synopsys Design Compiler library for the company’s programmable core cell.

BS/MS in Software Engineering or Electrical Engineering, Proficient C and/or C++ code developer, Proficient knowledge of synthesis tools and demonstrated ability to generate cell libraries., Knowledge of LUT based FPGA cell models