SW Infrastructure Engineer

Great opportunity to join Pre-Ipo creating the standard in Programmable IP for the communications infrastructure!

Responsible for development of synthesis libraries for use in ASIC design environments. Initial requirement will be to develop synthesis libraries for various synthesis tool vendors to support the company’s programmable core cell.

BS/MS in Software Engineering or Electrical Engineering Proficient C and/or C++ code developer Proficient knowledge of synthesis tools and demonstrated ability to generate cell libraries. Knowledge of LUT based FPGA cell models