Digital Flow Enablement Solutions Architect

• Leading customer engagements on standard cell library optimization and RTL->GDS enablement, including techLEF creation and updates, mapping files, and general flow development.

• Interfacing with customers regarding digital flow enablement and methodologies, including:

• timing characterization, including sensitivity modeling,

• Physical view generation (LEF, GDS, abstracts, etc)

• Logical view generation (LIB, CDL, Spectre, etc)

• Technology LEF creation for digital tools

• MSOA flows

• Performing design of experiments and running Genus/Innovus to validate techLEF correctness and library performance and DRC correctness

• Tempus timing flow development and validation

• Working closely with R&D on tools and methodology improvements

• Other digital P&R tasks as needed by the group

• Processes nodes range from 1.4nm to 350nm, with majority of work at GAA advanced nodes

• Bachelor’s degree with at least 12-16 years of design/EDA experience or Master’s degree with at least 10 years of experience. Master’s degree preferred.

• Knowledge of standard cell and IO design, optimization and characterization methodology including LLE/LDE effects

• Excellent digital simulation and debug skills

• Experience with techLEF development at advanced nodes a must

• Understanding of Liberty (.lib), Verilog & other views, such as NLDM, CCS & ECSM

• Strong knowledge of Digital Design flows and Static Timing Analysis

• Prior experience with ASIC digital implementation flows and EDA tools is required

• Experience with advanced nodes (5nm and below) required.

• Good programming knowledge in Unix, Shell scripting, perl and importantly TCL

• Strong customer-facing communication and problem solving skills

• Strong personal drive for continuous learning and expanding professional skill sets

• Excellent verbal and written communication skills

Familiar with EDA tool:

• Characterization: Liberate, Liberate MX, Liberate AMS

• Simulators: Spectre, AMS, Xcelium

The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.