FPGA DevOps Engineer

• Operate and maintain AMD Vivado and Vitis toolchains for FPGA/SoC development (Zynq, Versal).
• Automate synthesis, implementation, IP integration, bitstream generation, and platform export using Tcl and Python.
• Design, implement, and maintain DevOps pipelines using tools such as GitLab CI, Jenkins, or GitHub Actions, with workflows described in YAML.
• Integrate HDL/RTL codebases (Verilog/VHDL/SystemVerilog) into version-controlled, testable, and deployable pipelines.
• Develop robust scripting and automation solutions for toolchain orchestration, artifact packaging, and deployment.
• Support and extend build/test infrastructure for both firmware and hardware components across heterogeneous targets.
• Maintain consistent and reproducible environments using containers (Docker) or virtualization technologies.
• Collaborate with software, hardware, and QA teams to ensure seamless handoff and traceability of artifacts across development stages.

Do you have experience in Version control systems?, Do you have a Master’s degree?, FPGA DevOps Engineer

Must be U.S. citizen due to U.S. Government contract requirements.

Must be eligible to obtain and maintain a DoD Secret clearance. Active clearance preferred., * Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• Program and automate workflows.
• Strong scripting skills in Python and Tcl for automation of FPGA workflows.
• Experience designing CI/CD pipelines using Azure DevOps Server and Git-based source control repositories.
• Experience utilizing Docker for containerized application development and deployment.
• Familiarity with software quality practices, including static code analysis, dynamic analysis, and automated quality gates within the development pipeline.
• Proficient with Git and collaborative version control practices.
• Experience building and maintaining software build systems and toolchains.
• Proficiency with build automation tools such as CMake, GCC, or Similiar development/build environments.
• Experience with static code analysis tools such as Coverity, CodeSonar, or similar tools.
• Experience integrating code coverage metrics and quality gates into CI/CD pipelines.
• Ability to design, maintain, and monitor automated build and analysis pipelines to ensure software quality standards are met.
• Solid understanding of FPGA development flow and related deliverables: IP packaging, synthesis, timing closure, and bitstream export.
• Familiarity with Linux environments and Bash scripting., * Programmable Logic (PL) background exposure to Xilinx Vivado, ability to partner with PL teams on build / test automation for bitstreams.
• CompTIA Security+
• Operating in controlled / tiered engineering environments: Familiarity with CI/CD across restricted networks and one-way transfer patterns., * This position requires the ability to obtain and maintain a U.S. Government security clearance. Are you a U.S. citizen? (Yes/No)

Ability to Commute:

• Layton, UT 84040 (Preferred)

Pulled from the full job description

• 401(k)
• Health insurance
• 401(k) matching
• Paid time off
• Vision insurance
• Dental insurance
• Flexible spending account, * 401(k)
• 401(k) matching
• Dental insurance
• Employee assistance program
• Flexible spending account
• Health insurance
• Life insurance
• Paid time off
• Relocation assistance
• Vision insurance