Lead Software Engineer

Candidate will be responsible for software development and validation of PCIe Verification IP. As a Lead Software Engineer, candidate is expected to participate in development efforts of the PCIe product to meet customer use model, solution requirements, protocol specification and execute necessary SW development practices to create reusable robust software solution to enable verification of these interface protocols. Candidate should be able to work with multi-site and diverse team. You need to effectively collaborate multi location development team to contribute in PCIe verification IP development, milestones technical roadmap and people training for success.

The candidate is also expected work with technical support lead and key customers to resolve implementation or usage issues as Cadence VIP products are used within various verification environments and timing critical to our customer’s successes.

Our VIP PCIe R&D team is looking for a self-motivated, hands-on, and creative Lead Software Engineer who can be part of PCIe verification IP team and development efforts of the most complex industry leading software solutions for hardware/SOC memory and protocol verification. This industry-leading and proven technology is critically important for state-of-the-art products that are existing or under development, * BS with a minimum of 4 years of experience OR MS with a minimum of 2 years of experience OR new PhD Graduate

• Extensive experience in modeling in C/C++ and background in object-oriented, algorithms, and data structures.
• In-depth understanding of space/time complexity and advanced debugging techniques for proficiency in troubleshooting software issues and debugging a large codebase.
• Strong analytical and problem-solving skills with an ability to visualize processes and outcomes.
• Outstanding all-round communication skills and ability to work collaboratively in a dynamic multi-location environment.

Strong Plus:

• Working knowledge of PCI Express (PCIe) protocol or one or more protocols USB, NVME, SATA, Display Port, etc.
• Knowledge of Verilog/SystemVerilog languages and OVM/UVM verification methodologies.
• Experience with digital logic design or IP/SoC level Verification flow.
• Customer orientation and knowledge of the EDA tool flow.

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is the industry leader of Verification IP (VIP) with products supporting several communication protocols and memory interfaces. Cadence VIP fits into nearly every verification environment with support for all major simulators and verification languages. Our VIP delivers the advanced features that you need to maximize your productivity and keep projects moving forward.