Digital Design Engineer Semiconductor (all gender)

ALTEN GmbH
1 month ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English

Job location

Tech stack

Logic Synthesis of Circuits
Static Timing Analysis
SystemVerilog
VHDL
Information Technology

Job description

  • adapt and enhance existing IP modules to support new features and requirements
  • set up and execute logic synthesis, including constraint management
  • perform implementation verification using Spyglass and Logic Equivalence Checking (LEC)
  • conduct power simulations and analyze results
  • Prepare comprehensive design documentation.

Requirements

  • have completed degree in Electrical Engineering, Computer Science, Physics or similar studies
  • have proven experience in RTL design and verification (SystemVerilog, VHDL)
  • have a strong background in logic synthesis, timing analysis, and power simulation
  • have experience with industry-standard tools: Spyglass, DesignCompiler, LEC, Xcelium, ATPG
  • have good communication skills in English

Benefits & conditions

  • Work life balance - flexible working hours and mobile working possible
  • Fit and relaxed - with EGYM Wellpass
  • Enjoy biking - always on tour with bike leasing
  • Green Mobility - with us you can travel at a reduced rate

…in addition we offer a permanent employment contract, corporate benefits and team events.

About the company

As one of the world's leading engineering service providers, we at ALTEN are committed to positively shaping the future of our partners, the careers of our employees and the challenges facing our society and environment. More than 50,000 employees in 30 countries are already working on innovative solutions in various engineering and IT sectors such as automotive, aerospace, renewable energy, medical technology and railway technology.

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