ASIC / NoC SoC deployment architect - Qualcomm - Guyancourt, France

The QITC mission is to develop and deploy custom-built interconnect hardware IPs, software tools, and exploration and verification methodologies so that SoC integration teams can quickly assemble SoCs with the desired Power Performance Area (PPA) characteristics. To this end, QITC technology embraces the complete SoC infrastructure to provide increased SoC performance at minimal cost for integration. Our work is at the backbone of the SoC, interconnecting all major IP solutions. You will join the solutions deployment team with the mission of deploying and supporting the QITC NoC technology across all the SoCs of Qualcomm portfolio (Mobile, Automotive, Servers, IoT, Connectivity, etc..).

This is a challenging position, working on most innovative technologies, surrounded by experts but also by users of our technology all over the world and from various teams (SoC Architecture, HW and SW Design, Verification, Debug, Post Silicon).

Responsibilities

In your role, you will:

• Collaborate regularly with highly skilled experts across different teams (Architecture, Hardware, software, verification, emulation, ...) to ensure our technology is used efficiently in Qualcomm SoCs
• Contribute to the definition of interconnect requirements and configuration in the various SoCs
• Be responsible for the technical support of new QITC solutions
• Help resolving NoC micro-architecture and NoC integration issues
• Participate in defining new solutions and improvements for our technology
• Develop in-depth technical material and organize trainings for different teams worldwide

Do you have experience in Python?, Do you have a Master's degree?, * Strong understanding of overall SoC development flow: SoC architecture, RTL design and verification, SoC performance and DDR memory channel, physical implementation, silicon debug.

• Good knowledge in system level features such as memory-mapping, MMUs, Quality of service, cache infrastructure, security schemes, etc..
• Strong analytical skills for debug in simulation, emulation or silicon bring-up environments.
• Understand of interconnect protocols like AHB/AXI/ACE/ACE-Lite/CHI/NoC concepts.
• Python & Perl scripting
• Ability to quickly react and adapt to changes.
• Excellent communication skills., * Master's degree in Microelectronics, Computer Science, or related field.
• Preferably 5-10 years of solid experience in design, architecture and/or application engineering in SoC/ASIC development cycle.
• Standard SoC knowledge: Multimedia Ips, GPU, multi-core CPU architecture, Processors, Caches, memory controller, interconnects, ... and related design, integration and verification challenges

Preferred Qualifications

One or multiple qualifications in the below list would be a great advantage:

• SoC high speed protocols and chiplet architectures
• Coherency protocols

Keywords

• SoC, ASIC, Deployment, Solutions Architect, Interconnect, Cache, CPU, GPU, Coherency, debug, verification, * Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience., Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field.

• References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.