Staff Digital Design Engineer
Role details
Job location
Tech stack
Job description
- Architecting, designing, and implementing digital IP blocks and subsystems for our neuromorphic SoCs.
- Translating high-level product and algorithmic requirements into RTL-level specifications and microarchitectures.
- Owning all front-end design activities, including RTL coding (SystemVerilog/Verilog), synthesis, STA, simulation, and design documentation.
- Collaborating closely with verification and backend engineers to align functionality, constraints, and design intent.
- Defining and optimising PPA (Power, Performance, Area) goals across IPs and subsystems.
- Developing design flows and automation scripts (Python/shell scripting) to improve productivity and consistency.
- Applying low-power design techniques and contributing to overall SoC-level integration.
- Writing and maintaining documentation, including IP specifications, design intent, and integration guides.
- Mentoring junior engineers, contributing to code reviews, and fostering a culture of technical excellence and collaboration.
Requirements
Do you have experience in Verilog?, * 6+ years of hands-on ASIC digital design experience, owning complex IPs through the full lifecycle.
- Strong expertise in front-end digital design, including Verilog/SystemVerilog RTL development and debugging.
- Solid understanding of SoC architecture, bus interfaces, and IP integration flows.
- Experience performing synthesis and static timing analysis (STA) and defining timing constraints.
- Proven experience with Cadence tools and industry-standard EDA flows.
- Strong understanding of low-power design techniques and PPA trade-offs.
- Proficiency in Python and shell scripting for design flow development and automation.
- Excellent documentation skills from drafting specifications to design intent and integration documentation.
- Strong cross-functional collaboration mindset
- Excellent problem-solving and debugging abilities, with an analytical approach to complex design challenges.
Nice-to-haves:
- Experience with FPGA prototyping (Vivado or similar).
- Familiarity with DFT, synthesis, and STA flows.
- Knowledge of communication protocols such as SPI, I2C, or AMBA.
- Exposure to C/C++ for test or integration code.
- Experience contributing to design methodology or flow development.
- Prior experience mentoring or coaching junior engineers.
Benefits & conditions
At Innatera, you'll be part of a pioneering team building the next generation of brain-inspired processors for edge AI. Your work will help bring groundbreaking technology to life, powering intelligent devices with real-world impact, from healthcare to consumer electronics.
- Competitive salary.
- Pension plan.
- A flexible working environment (work-from-home policy, flexible working hours, advantageous holidays scheme) Note: We work from the office 3 days per week.
- A generous holiday scheme.
- A collaborative, ambitious team with the freedom to innovate.
- An inclusive culture that values openness, curiosity, and personal growth.
- Office perks like fresh fruit, snacks, and an on-site gym.
- Statutory commuting/home allowance.
From engineering and machine learning to sales and non-engineering teams - whatever your expertise, your contributions will shape our growth.
Whether you're passionate about microarchitecture, excited by verification or physical design, driven by supporting operations, building strong teams, or mastering the details of accounting, we'd love to hear from you!