Senior Digital Design Engineer
Beagle
Barcelona, Spain
6 days ago
Role details
Contract type
Permanent contract Employment type
Full-time (> 32 hours) Working hours
Regular working hours Languages
English Experience level
SeniorJob location
Barcelona, Spain
Tech stack
Bash
C++
Logic Synthesis of Circuits
Perl
Python
PCI Express
Subversion
Tcl (Programming Language)
Verilog
VHDL
Application Specific Integrated Circuits
GIT
Software Version Control
Job description
- Own the architecture and lead the RTL implementation of PCIe subsystems
- Drive efficient interaction between the PCIe block and CPU clusters using AMBA-CHI coherency
- Integrate and verify IPs within large SoC environments
- Work closely with cross-functional teams of digital, verification, and architecture experts
Requirements
We're looking for an experienced engineer to take a leading role in the design and integration of PCIe solutions within complex SoC/ASIC environments. If you're passionate about microprocessor architecture, high-speed I/O, and building high-performance subsystems, this role puts you at the centre of it., * 4+ years industrial experience (Engineer) or 6+ years (Lead)
- Strong hands-on experience with PCIe (design and/or integration)
- Solid background in SoC/ASIC IP integration
- Proficiency in RTL design (Verilog or VHDL)
- Experience with basic block-level testing
- Familiarity with at least one protocol: AXI, CHI, or AHB
Nice to have:
- Master's degree or PhD
- Knowledge of C++, Python, Perl, Bash, or TCL
- Experience working with version control (git, svn)
- Understanding of coherency protocols
- Experience with CXL
- Exposure to common digital design tools (Synthesis, STA, CDC, Lint, etc.)
