Digital IP Design Engineer
Role details
Job location
Tech stack
Job description
Join our team at Apple Austria to develop and integrate Control IPs for the next generations of Cellular Transceiver SoCs!
As a member of our Cellular team in Linz, you will be responsible for crafting sophisticated digital IPs that control all major system components. You will collaborate closely with system architects, firmware teams, verification engineers, and other stakeholders to develop block-level specifications and implement the designs. You will own the creation of the blocks and guide them through the concept, design, integration, and verification phases., As a valued member of our Cellular Design Engineering team, you will be responsible for developing, integrating, and verifying IP sub-components for a cellular transceiver System on Chip. Your primary responsibilities will include defining and driving the implementation, timing closure, and power optimizations in close collaboration with a multi-disciplinary team comprising system, digital, analog, and firmware design, design verification, and physical design teams. These teams will provide the vital support to facilitate your daily work.
Your responsibilities will extend beyond design, encompassing end-to-end accountability throughout the project lifecycle of the IP developed from conception to design, verification, integration, silicon validation, and finally, in-field operation.
Requirements
Do you have a Master's degree?, Experience with synthesis, logic equivalence, or ECO techniques would be highly beneficial.
The ideal candidate demonstrates a strong passion for owning/driving design schedules using well-defined metrics, exhibiting initiative, and taking ownership of responsibilities.
Experience with AXI/AHB bus fabric and processor sub-systems would be a huge asset.
A bachelor's or master's in Electrical Engineering, Communication Engineering, Computer Science/ Software Engineering, or equivalent., Hands-on experience in developing structured RTL designs with System Verilog or VHDL.
Possesses outstanding RTL/Netlist debugging skills to effectively resolve technical challenges in simulation and silicon development.
Expertise in designing complex systems with Clock/Reset Domain Crossings and power domains.
Proficient in day-to-day usage of scripting languages (TCL, Python, Perl, shell), Linux, and revision control systems, database management, and releases.
Proven track record to meet ambitious deadlines and maintain productivity.
Excellent problem-solving skills and the capacity to find effective technical solutions between partners in RTL-design, firmware, system engineering, power, and physical design teams.
English language proficiency is required
Benefits & conditions
The minimum salary pursuant to the CBA amounts to EUR 66,676 gross per year for full-time employment. Actual salaries are oriented at current market salaries and take your qualifications and experience into account.
