3D Integration (Design for Test) Engineer

Our client is a globally recognized leader in ICT technologies with a strong commitment to innovation and scientific excellence. Located in Leuven, Belgium, their European Research Institute (ERI) serves as a strategic R&D center focused on enabling disruptive technologies through collaboration across international teams., * Conduct research on DFT (Design for Test) methodologies for digital logic chips, focusing on defect mechanisms, fault simulation, and failure analysis.

• Develop DFT testing methodologies for 3DIC chips and conduct research on related defect mechanisms, fault simulation, and failure analysis.

• Explore DFT testing strategies for memory (including NVM) and analog IP, with emphasis on defect modeling and failure mechanisms.

• Drive end-to-end DFX architecture and test implementation, supporting lifecycle reliability and failure localization.

• Master's or PhD in Electronics, Microelectronics, Communications, Automation, Semiconductor Engineering, Mathematics, Physics, Chemistry, or related fields.

• Familiar with DFT technologies including MBIST, SCAN, and ATPG.

• Knowledge of digital and analog fault mechanisms and testing algorithms.

• Research experience in digital defect modeling, fault simulation, and failure analysis.

• Hands-on work with 3DIC/IO interconnect testability and reliability modeling.

• Experience in memory and analog DFT defect modeling and fault analysis.

• Strong background in system-level DFX strategy and failure localization techniques.

• 5-10 years of relevant experience in DFT, reliability analysis, and semiconductor design or integration.

If you are excited by the challenge of shaping the future of 3D integration and design-for-test in advanced semiconductor systems, we encourage you to apply. Join a pioneering research environment where your expertise will directly contribute to next-generation innovation, in a role that offers both technical depth and global impact.