Digital Ic Verification Engineer

Join a thriving environment tasked with delivering new and disruptive technologies! We are looking for a Digital IC Verification Engineer with hands-on experience using Cadence verification tools to verify complex digital ICs and SoCs. The role focuses on building high-quality verification environments, executing simulation and coverage-driven verification, and ensuring design correctness prior to tape-out. Key Responsibilities * Develop verification plans from design specifications and micro-architecture documents * Build and maintain SystemVerilog/UVM testbenches using Cadence verification flow * Write directed and constrained-random tests to validate RTL functionality * Develop and integrate SystemVerilog Assertions (SVA) * Execute simulations and regressions using Xcelium * Debug functional failures using SimVision and waveform analysis * Perform functional, code, and assertion coverage using IMC (Integrated Metrics Center) * Achieve coverage closure and support verification

sign-off * Collaborate with design engineers to identify, debug, and resolve RTL issues * Perform CDC/RDC analysis using Cadence JasperGold or Conformal CDC (if applicable) * Support low-power verification using UPF * Participate in design and verification reviews and provide sign-off reports Qualifications * Bachelor's or Master's degree in Electrical / Electronics / Computer Engineering * Strong understanding of digital design fundamentals (timing, FSMs, pipelines, clocking, resets). * Proficiency in SystemVerilog and UVM. * Hands-on experience with Cadence Xcelium simulation tool. * Experience with IMC for coverage analysis and closure. * Familiarity with SimVision for debug and waveform analysis. * Understanding of assertion-based verification (SVA). * Knowledge of coverage-driven verification methodology Nice To Have * Experience with Cadence JasperGold (formal verification, CDC, RDC) * Familiarity with low-power verification using UPF * Experience verifying standard protocols (AXI, AHB, APB, PCIe, etc.) * Knowledge of Cadence VIPs * Scripting experience in Python, Perl, or TCL * Experience with SoC-level verification, emulation, or Palladium Cadence Tools & Technologies * Xcelium - Simulation and regression * SimVision - Debug and waveform analysis * IMC - Coverage analysis and closure * JasperGold - Formal verification, CDC/RDC * VIP Catalog - Protocol verification IP * Palladium - Emulation (optional) * Senior: 7+ years (verification architecture, sign-off responsibility) * Strong debugging and analytical skills * Clear written and verbal communication * Ability to work effectively in cross-functional teams Why Join Us At The TMRW Foundation SILICON - you will be part of a dynamic and innovative team that is dedicated to building cutting-edge technologies. We offer a collaborative and inclusive work environment where your contributions will make a significant impact. You can send your CV to ******.