Senior Digital Design Engineer
Beagle
Barcelona, Spain
6 days ago
Role details
Contract type
Permanent contract Employment type
Full-time (> 32 hours) Working hours
Regular working hours Languages
English Experience level
SeniorJob location
Barcelona, Spain
Tech stack
Bash
Logic Synthesis of Circuits
Perl
Python
Subsystems
Subversion
Systems Integration
Tcl (Programming Language)
Verilog
VHDL
Scripting (Bash/Python/Go/Ruby)
GIT
Software Version Control
Job description
We are looking for a Senior Digital Design Engineer to design and develop high-performance memory subsystems for modern SoCs. You will work within the Memory Design Team and collaborate closely with other engineers to create efficient and robust memory architectures., * Define, design, and implement memory controllers and subsystems (DDR, HBM)
- Develop and verify RTL (Verilog or VHDL) for memory blocks
- Work with timing constraints and perform block-level testing
- Integrate memory IPs into SoC environments
- Collaborate with cross-functional teams to ensure coherency and high-performance operation
Requirements
- 8+ years of industrial experience in digital design
- Strong knowledge of DDR or HBM memories
- Proven experience designing or integrating memory controllers
- Hands-on experience with AXI protocol
- Proficiency in RTL design (Verilog or VHDL)
- Experience with timing constraints and basic block-level testing
Desired:
- Master's degree or PhD
- Scripting skills (Python, Perl, Bash, TCL)
- Experience with version control (git, svn)
- Knowledge of coherency concepts and protocols
- Experience defining memory maps