Staff Digital Design Engineer
Role details
Job location
Tech stack
Job description
optimize advanced DSP algorithms and circuits for 200+Gbps SerDes for lowest static and dynamic power consumption. Your work will directly impact the performance of AMD's next-generation connectivity solutions for markets such as data center networking and wireless telecommunications. THE PERSON: You are a collaborative team player with deep expertise in digital circuit power analysis, optimization and practical implementation. You communicate effectively across hardware and algorithm teams, and thrive in a fast-paced, cross-site environment. Your analytical skills and commitment to continuous learning enable you to solve complex problems with novel solutions, elevating the team's capabilities., * Collaborate with architects, hardware engineers and verification engineers to define, refine and implement low power DSP features for cutting-edge and next-generation SerDes transceivers
- Model and evaluate equalization, filtering and sequence detection algorithms for power efficiency
- Contribute to RTL development, using front-end ASIC tools to ensure the highest quality code
- Contribute to power testcase creation with verification engineers
- Develop comprehensive documentation detailing power optimization approaches
Requirements
- Proven experience in power analysis and optimization of digital logic at advanced process nodes
- Strong background in digital design techniques, RTL (preferably SystemVerilog)
- Experience with PowerArtist and/or PPRTL tools, scripting and flows
- Familiarity with ASIC front-end design tools and flows, in particular vectored power analysis and gate-level simulation
- Familiarity with equalization techniques such as FFE, CTLE, DFE or MLSE and their implementation would be an advantage
EDUCATION: BSc or Masters in Electronics, Electrical or Computer Engineering, or related field.