Digital Validation Engineer - FPGA design

8 -10 years in FPGA design and validation

• Experience in FPGA flow to take the design, adapt it and generate FPGA bit files. Masters the full FPGA flow from RTL to electrical validation

• Understands and develops timing constraints specific to FPGA and analyses timing reports for the given design in consultation with design team.

• Proven experience in digital design concepts and code development in VHDL/Verilog/system Verilog.

• Good understanding of timing issues in FPGA flow and how to address them, including clock domain crossings, clock generation, combinatorial loops.

• Proven experience with Synplify Synthesis tool, Vivado Place and Route Tool, Xilinx FPGAs

• Experience in writing C based tests for the FPGA testing.

• Experience in Python based code development.

• Experience in debug tools associated with FPGA debug.

• Strong experience in electronics fundamentals and debug.

• Ability to perform Device debug / Board debug and identify root cause, within an electrical validation environment.

• Need to be thorough at bench level validation Oscilloscope and digital analyzers.

• Familiar with revision control tools (SVN, run compute jobs)