Staff Engineer Functional Digital Verification iv)

Infineon
Villach, Austria
2 days ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Experience level
Intermediate
Compensation
€ 61K

Job location

Villach, Austria

Tech stack

Adobe InDesign
Analogue Electronics
Software Debugging
Hardware Description Language
Python
SystemVerilog
GIT
Information Technology
Programming Languages

Job description

Job IdHRC1399990JobfamilieResearch & DevelopmentBeschäftigungsartVollzeitVertragsdauerUnbefristetEinsteigen alsBerufserfahrene*r (inkl. Management Positionen)#WeAreIn for jobs that impact everyone's life. Join the thinkers, builders, and problem solvers behind tomorrow's technology. As a Functional Digital Verification Engineer on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Are you in?, * Create and define verification plans, for digital verification of Mixed Signal designs

  • Create new and improve existing verification environments in SystemVerilog language using Universal Verification Methodology (UVM) and Constrained Random approach
  • Execute tests in these environments on RTL and gate-level and debug issues in design and verification environments
  • Closely cooperate with analog and digital designers as well as concept and other verification engineers
  • Mentoring of junior colleagues, consultants, and students

Your profile You work conscientiously on making things better, faster, and more efficient and keep up high quality standards for yourself and other people. You can solve technical problems and work independently. You are a team player and support your colleagues for the overall team and company success.

Requirements

  • A university degree in Electrical Engineering, Computer Science, Information Technology, or a similar academic discipline
  • Ideally 3-5 years of related work experience
  • Excellent know-how with UVM, especially using System Verilog
  • knowledge of RTL design (HDL) and digital or analog circuits
  • knowledge of Cadence verification software (Xcelium and vManager) or similar
  • knowledge of GIT, Python, and other programming languages as a plus
  • Fluency in English

Benefits & conditions

We offer competitive salaries and additional benefits based on your performance, experience and qualification. The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group G (https://www.feei.at/aktuelles/mindestloehne-und-gehaelter-eei/). The monthly salary is paid 14 times p.a. We offer a higher compensation depending on your expertise and skills.Apply to this position online by following the URL and entering the Job ID in our job search.https://www.infineon.com/jobs Angaben des Unternehmens gemäß Gleichbehandlungsgesetz: Das Mindestentgelt für die Stelle als Staff Engineer Functional Digital Verification (f/m/div) beträgt 4.341,85 EUR brutto pro Monat auf Basis Vollzeitbeschäftigung. Bereitschaft zur Überzahlung.

About the company

We make life easier, safer and greener, with technology that achieves more, consumes less and is accessible to everyone. Microelectronics from Infineon is the key to a better future. Efficient use of energy, environmentally-friendly mobility and security in a connected world we solve some of the most critical challenges that our society faces while taking a conscientious approach to the use of natural resources. 2 Staff Engineer Functional Digital Verification (f/m/div)

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