Staff Digital Design Verification Engineer
Role details
Job location
Tech stack
Job description
As a member of the UK Digital Design team, the Staff level Digital Design Verification Engineer will work on the next generation mixed signal optical devices for Semtech's Signal Integrity Products (SIP) team, leading complex verification efforts for our advanced digital cores. This role requires technical expertise in verification methodologies, strong leadership capabilities, and the ability to drive verification quality across multiple projects concurrently., * Verification Leadership You will lead the development and execution of comprehensive verification strategies for complex digital IP blocks and subsystems. This includes defining verification plans, creating testbench architectures, and establishing coverage goals that ensure first-silicon success. You'll mentor junior engineers, conduct design and code reviews, and establish best practices across the verification team.
- Technical Execution You will develop advanced testbenches using SystemVerilog and potentially UVM, create constrained-random test sequences, and build functional coverage models. Working closely with design teams, you'll identify and resolve complex bugs, perform protocol compliance verification, and develop reusable verification components. You'll also evaluate and integrate new verification tools and methodologies to improve efficiency and coverage.
- Cross-Functional Collaboration You will work with architecture, design, software, and physical implementation teams to ensure verification requirements are met throughout the development cycle. This includes contributing to architecture reviews, coordinating with emulation and FPGA prototyping efforts, and supporting post-silicon validation activities.
Requirements
Do you have experience in SystemVerilog?, Do you have a Master's degree?, * Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or related field
- 6+ years of experience in digital IC verification
- Expert-level proficiency in SystemVerilog and UVM methodology
- Strong understanding of digital design concepts, microarchitecture, and RTL design
- Proven track record of successful tape-outs and verification closure
- Proficiency with simulation tools (Xcelium, Questa, VCS) and debug tools (Verdi etc.)
- Experience with coverage analysis and closure methodologies
- Strong scripting skills (Perl, Python, or similar), * Experience with assertion-based verification and SystemVerilog Assertions (SVA)
- Experience with formal verification techniques and tools
- Knowledge of emulation and FPGA prototyping platforms
- Familiarity with low-power verification methodologies (UPF)
- Experience with continuous integration and regression management systems
Key Competencies
- Technical leadership and mentorship abilities
- Excellent problem-solving and debugging skills
- Strong communication skills for cross-functional collaboration
- Ability to manage multiple priorities and drive projects to completion
- Self-motivated with ability to work independently and in team environments
- Commitment to quality and attention to detail