Graduate Engineer - Digital Backend (RTL to GDS), Cadence Flow
Role details
Job location
Tech stack
Job description
As a Graduate Digital Backend Engineer, you will participate in the end-to-end physical implementation of complex SoC and mix-signal designs. You will work within an experienced backend team and learn how to transform RTL code into a tape-out-quality GDSII database using the Cadence digital implementation tool suite. The role spans the complete backend flow including synthesis, floorplanning, power planning, place & route, timing closure, physical verification, and sign-off.
You will receive structured coaching, access to internal training material, and the opportunity to work on real production designs while gradually taking ownership of specific blocks.
- RTL Synthesis (Cadence Genus)
- Run logic synthesis and generate optimized netlists according to timing, area, and power constraints.
- Perform constraint development and validation (SDC).
- Analyze synthesis reports: timing, area, power, QoR, and identify optimization opportunities.
- Collaborate with RTL and verification teams to resolve structural issues.
- Floorplanning & Power Planning (Cadence Innovus)
- Assist in creating initial chip and block floorplans, including die/core sizing, aspect ratio, macro placement, and I/O planning.
- Support power grid (PG) design, power rail planning, and IR-drop-aware placement.
- Ensure integration of physical IP (memories, analog blocks, hard macros).
- Placement, Clock Tree Synthesis & Routing
- Run placement, CTS, and detailed routing using Cadence Innovus.
- Perform optimization iterations for timing, congestion, and power.
- Implement design-for-manufacturability (DFM) and power-intent (UPF) guidelines.
- Ensure correctness of CTS: skew, slew, balancing, and power efficiency.
- Static Timing Analysis (Cadence Tempus)
- Analyze and resolve setup/hold violations across multiple modes and corners.
- Work with multi-corner, multi-mode (MCMM) analysis environments.
- Debug timing paths, parasitics, and cross-talk using Cadence sign-off flows.
- Power & IR-Drop Analysis (Cadence Voltus)
- Prepare power models and scenarios for dynamic and static IR-drop analysis.
- Perform EM/IR validation and support PDN optimization.
- Interpret results and propose improvements in PG design or standard-cell usage.
- Physical Verification (Mentor Calibre)
- Run DRC, LVS, and ERC checks on full layouts.
- Debug physical verification violations and collaborate with layout engineers.
- Ensure the design meets manufacturing requirements and PDK guidelines.
- Sign-off, ECO Handling & Final GDSII Output
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Execute ECO cycles using Cadence Innovus/Genus ECO flows.
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Validate timing, power, signal integrity, and physical verification after ECOs.
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Prepare the final, tape-out-ready GDSII database.
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Support documentation and sign-off reviews for tape-out, * Structured onboarding and mentorship by experienced Senior Engineers.
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Hands-on work on real production ASICs/SoCs.
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Access to industry-standard EDA tools (Cadence Genus/Innovus/PrimeTime).
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Career growth path toward Physical Design Engineer or Implementation Lead.
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Opportunity to contribute to tape-outs across multiple technology nodes., We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning. Job title : Graduate Engineer - Digital Backend (RTL to GDS), Cadence Flow (f/m/d)
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Department Manufacturing
Requirements
Do you have experience in Verilog?, Do you have a Master's degree?, * Master's or Bachelor's degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
- Solid understanding of CMOS fundamentals, digital design, and VLSI basics.
- Familiarity with Verilog/VHDL, SDC constraints, and Unix/Linux workflows.
- Basic exposure to scripting languages (TCL, Python, or Perl).
- Strong analytical thinking and problem-solving skills.
- Proactive, collaborative, and eager to learn.
Nice-to-Have Skills
- Knowledge of RTL synthesis or P&R concepts through academic projects or internships.
- Understanding of timing analysis, STA concepts, or physical verification.
- Experience with any EDA tool (Cadence, Synopsys, Mentor).
