Digital Design Engineer

Eu Recruit
Paris, France
16 days ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Experience level
Senior

Job location

Paris, France

Tech stack

Microarchitecture
Logic Synthesis of Circuits
Ethernet
Python
PCI Express
Reduced Instruction Set Computing
System on a Chip
SystemVerilog
Tcl (Programming Language)
Verilog
VHDL
Scripting (Bash/Python/Go/Ruby)
Backend
GIT

Job description

  • Architectural Leadership: Collaborate with project leads to define IC architecture, verification methodologies, and micro-architecture specifications.
  • End-to-End Design: Lead the journey from RTL to Netlist, designing complex blocks and integrating high-level IPs and various RTL components.
  • Technical Quality: Execute rigorous LINT/CDC/RDC checks and write SDC constraints for logical synthesis to ensure "first-time-right" silicon.
  • Cross-Functional Synergy: Partner with DFT and Back-End teams to optimize the physical implementation for the best possible area/power trade-off.
  • Project Governance: Animate design reviews, document processes according to QA policies, and provide KPI-driven progress reports to Program Management.
  • Silicon Validation: Take your designs further by participating in the hands-on evaluation of manufactured ICs in our measurement lab.

Requirements

As a Senior Digital IC Design Engineer, you will be a driving force in the design team, taking technical ownership of complex digital work-packages. You won't just be executing tasks; you will be defining the architecture and implementation strategies for state-of-the-art Integrated Circuits (ICs) in deep-submicron CMOS technologies., * Core Expertise: Deep knowledge of Digital IC & SoC design, specifically within ARM or RISC-V platforms.

  • Protocol Proficiency: Solid experience with high-speed serial interfaces such as JESD204, Ethernet, or PCIe.

  • Full-Flow Vision: A comprehensive understanding of the entire flow from RTL to GDSII.

  • The "Mixed-Signal" Edge: You understand the "Analog side of the fence," particularly A/D and D/A converters or RF transceivers.

  • Toolbox: Expertise in SystemVerilog, VHDL, or Verilog. High proficiency with Cadence, Synopsys, or Siemens EDA flows, alongside Python/TCL scripting and Git.

  • Education: MSc or PhD in Electrical Engineering or a related field.

  • Language: Fluent in English (written and oral).

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