Engineer, Digital Verification

• Develop comprehensive verification plans for complex digital modules at IP, Subsystem, and SoC levels
• Design and implement reusable testbench components, including drivers, monitors, and scoreboards using SV-UVM
• Work closely with design teams to achieve coverage closure
• Coordinate with silicon test and evaluation teams to develop and deliver test patterns

• Extensive hands-on experience (3+ years) in digital verification using SystemVerilog (SV) and UVM methodology
• Experience in developing verification plans for complex digital blocks
• Experience in creating testbench environments at IP and/or Subsystem level
• Experience in constrained random stimulus and coverage closure
• Strong debugging skills and analytical problem-solving capabilities
• Familiarity with ARM-AMBA protocols
• Advantageous: Experience in formal verification and SystemVerilog Assertions (SV-Assertion) coding
• Advantageous: Exposure to Ethernet standards

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at and on LinkedIn and Twitter (X).