Staff Silicon Design Engineer
Role details
Job location
Tech stack
Job description
Role Overview We are seeking a hands-on technical leader to drive the development of advanced modeling infrastructure and architectural exploration for next-generation computing platforms. This role focuses on building scalable performance modeling collateral, enabling novel compute architectures, and aggregating insights to propose architectural changes that deliver dramatic improvements in performance, power, area (PPA) and user experience.
You will work closely with internal technical leaders to align architectural vision with product roadmaps spanning 7-10 years, ensuring strategic coherence across silicon, packaging, and software., * Infrastructure & Modeling Development:
- Architect and implement robust modeling frameworks for design space exploration (DSE) and performance analysis.
- Develop cycle-accurate, analytical, and AI-driven models to evaluate complex workloads, including ML and graphics/rendering.
- Architectural Innovation:
- Aggregate modeling insights to propose disruptive architectural changes across CPUs, GPUs, accelerators, interconnects, and memory hierarchies.
- Drive vision for dramatic increases in ML model concurrency and assess system-level impacts.
- Cross-Domain Technical Leadership:
- Bridge hardware, software, ML, and graphics domains to enable holistic architectural strategies.
- Collaborate with silicon design, packaging, compiler, and runtime teams to ensure end-to-end optimization.
- Strategic Alignment:
- Partner with internal technical leaders to align architectural exploration with long-term product roadmaps and technology investments.
- Software Development Leadership:
- Understand contemporary software development processes (Agile/Scrum).
- Lead daily standups, prioritize and drive issues and new features to closure.
- Ensure correct test infrastructure and CI pipelines are in place and executing properly to meet tactical sprints and epics.
- Tooling & Automation:
- Champion scalable infrastructure for automated DSE campaigns, visualization, and multi-dimensional trade-off analysis., AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.
Requirements
- Full-stack understanding from silicon implementation (including advanced packaging) to software and runtime interactions.
- Modeling & Programming Skills:
- Fluent in C++, low-level frameworks, and capable of generating modeling content.
- Strong grasp of x86 and RISC-V assembly, ISA design, modifying toolchains and executables, compilers, and performance tuning.
- Cross-Domain Proficiency:
- Ability to bridge hardware, software, ML, and graphics/rendering domains.
- Architectural Insight:
o Proven experience in design space exploration and quantifying PPA trade-offs.
- Vision for ML & Concurrency:
- Expertise in scaling ML workloads and understanding system-level implications of high concurrency.
- Software Process Leadership:
- Experience leading Agile teams, managing sprints, and ensuring CI/CD best practices., * Experience with industry-standard modeling frameworks (e.g., gem5, SST).
- Background in hardware/software co-design and full-system performance analysis.
- Familiarity with advanced packaging technologies and heterogeneous compute architectures.
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