Senior System Architect
Role details
Job location
Tech stack
Job description
The Applied Network Technology Lab (ANTL) in Munich is expanding its research activities in next-generation Ethernet and high-speed interconnect technologies for data center networks. A key focus area is the physical layer (PHY), where increasing data rates introduce new challenges in signal integrity, non-linearities, and system-level optimization. We are seeking an experienced and innovative network researcher to develop system-level models, explore architectural trade-offs and contribute to future physical layer solutions. Join the ANTL Ethernet Team as a Senior System Architect (m/f/d) Your mission · Develop and maintain an end-to-end PHY system model covering channel behavior, TX/RX impairments, Data converter abstraction and their associated non-idealities. · Drive architecture trade-off studies across resolution, sampling rate, power, BER and latency constraints. · Evaluate equalization and signal processing strategies under realistic impairments and limitations imposed by the non-ideal system. · Focus on system-level performance optimization by integrating advanced behavioral models including impairments to ensure system-level accuracy and predictive capability. · Translate complex simulation results into clear data-driven design recommendations, system-level constraints and engineering insights. · Monitor and comprehend advancements in Ethernet technologies, analyze standards (e.g. IEEE 802.3, UEC, OIF, MSA), assess their implications and identify opportunities for innovation and strategic advancement. · Shape technical positions in standards discussions such as IEEE, UEC - based on data-driven analysis. · Provide technical mentorship and guidance to junior engineers and provide leadership in technical discussions and reviews. · Contribute to the external research and standards ecosystem through engagement with leading conferences and collaboration with academic and industrial partners. Your profile/areas of expertise
Requirements
· Master's and/or PhD degree in Electrical/Electronic Engineering, Computer Science or related area. · Strong experience with high-speed PHY and SerDes systems, including experience with 100Gb/s per lane designs. · Demonstrated solid understand of channel modeling, equalization, jitter, noise and system-level data converter behavior. · Proficiency in system-level simulation using Python, Matlab or similar tools. · Ability to abstract complex physical effects into accurate and usable system models. · Ability to make sound engineering trade-offs under uncertainty and incomplete information. · Excellent intercultural communication skills, with proven ability to collaborate effectively across diverse teams and stakeholders. · Strong analytical mindset with the ability to translate theory into practical system insights. · Full professional proficiency in English (both written and spoken). German and/or Chinese knowledge is an advantage. Some travel activity should be expected as part of the position.