Senior Engineering Associate

Kforce has a client in San Jose, CA that is seeking a Senior Engineering Associate. In this role, the Senior Engineering Associate is responsible for collaboration with the offshore team, and offshore task coordination.

• Bachelor's degree
• 10+ years of experience with ASIC design activities - Verilog RTL, testcase debug, netlist checks, CDC checks, coverage analysis, timing closure, x-prop/gate level simulations
• 8-10 years of experience
• Domain knowledge in PCIE/CXL, DDR, AMBA AXI/APB protocols preferred
• Strongly prefer the ASIC experience; If FPGA is only experience, then domain knowledge is must