Forward Deployed AI Engineer

We are hiring Forward Deployed AI Engineers to embed inside enterprise customers’ silicon design environments and adapt Normal EDA to their data, workflows, and design challenges. You will work inside a pod with Deployment Strategy, Platform, other FDE, and GTM team members on a single enterprise engagement, and you will own the ML systems that make the platform work inside that customer’s environment., * Adapt Normal EDA to each customer’s proprietary data, design flows, and tooling. Validate generated artifacts against their specifications, and design evals against real customer workflows so model behavior holds up in production.

• Bridge between customer engineering artifacts and the ML systems that operate on them. You will need to understand both sides well enough to diagnose whether a problem is in the model, the data, or the workflow.
• Embed with silicon engineers at the customer. Translate their constraints back to Normal’s research, product, and platform teams, and shape what the platform becomes based on what you learn in the field.
• Make judgment calls on what to build, what to skip, and when to push back on a customer request that would compromise the quality of what ships. You will regularly operate ahead of a playbook.
• Codify what works on each engagement into reusable patterns that raise the floor for every engagement after yours.
• Bring field signal back to Normal’s core ML and product teams. Your read on what customers actually need will directly shape model and platform investment priorities.

Do you have experience in Verification (System development task)?, * Track record of shipping ML systems inside customer or production environments where model behavior had to hold up against real-world data. You may have been called an AI FDE, an Enterprise Tech Lead, or something else entirely.

• An interest in hardware, electrical engineering, and how chips get designed and built. If your background is in semiconductor verification, hardware engineering, or a related domain and you are building ML depth, that combination is a strong fit for this role.
• Willingness and ability to go deep on semiconductor verification workflows. You will spend significant time inside UVM testbenches, SystemVerilog codebases, and design specifications. Prior experience is a strong advantage, but what matters is whether you can build fluency fast and earn credibility with verification engineers.
• Strong software engineering fundamentals: proficient in Python, comfortable in production codebases, distributed-systems literate.
• Hands-on experience with the modern ML stack: prompt engineering, fine-tuning, evals, RAG, agentic patterns, model deployment.
• Calm in ambiguity. You make good decisions with incomplete information, and you know when to act and when to ask., * Direct experience with EDA, semiconductor design flows, verification workflows (UVM, SystemVerilog, coverage-driven verification), or other formal / structured engineering domains.
• Built or led an FDE or customer-deployment function from the ground up at an earlier-stage company.
• Open-source contributions or publications in AI or ML venues.