DFT Engineer/ SoC DFT Lead

SoC DFT Lead with experience to define, architect, and execute Design-for-Test solutions for complex multi-partition SoCs from RTL through silicon bring-up. The successful candidate will lead a team of DFT engineers and work closely with RTL, Physical Design, Validation, and Post-Silicon teams to ensure high-quality test implementation and coverage across the entire chip., * Define and document SoC-level DFT architecture and implementation strategy. Lead DFT execution across block, partition, and top-level integration.

• Architect and implement scan, scan compression, MBIST, LBIST, boundary scan, SSN, and iJTAG solutions. Plan and manage DFT requirements, schedules, netlist releases, and execution milestones.
• Coordinate with RTL, Physical Design, Timing, and Validation teams throughout the design cycle. Drive DFT insertion, verification, ATPG generation, fault coverage closure, and pattern signoff.
• Lead DFT structure verification, gate-level simulations, logic equivalence checks, and pattern retargeting activities. Analyze test coverage, diagnose failures, and support silicon bring-up and production ramp.
• Mentor and guide DFT engineers and provide technical leadership across projects. Participate in design reviews and ensure DFT readiness at all project milestones.

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field. 12+ years of experience in DFT with proven leadership of large SoC programs.
• Strong expertise in scan insertion, scan compression, ATPG, MBIST, LBIST, boundary scan, and gate-level simulation.
• Hands-on experience with Siemens Tessent tools and methodologies.
• Experience implementing and debugging SSN and iJTAG architectures. Strong understanding of multi-clock and multi-power domain SoC designs.
• Experience with DFT signoff, fault analysis, pattern validation, and silicon debug. Knowledge of synthesis, STA, formal verification, and physical design interactions.
• Proficiency with Verilog/SystemVerilog and scripting languages such as Tcl, Perl, or Python. Excellent communication, project coordination, and team leadership skills.

Preferred Qualifications

• Experience with advanced-node SoCs (7nm, 5nm, 3nm or below). Experience with chiplet-based or multi-die architectures.
• Familiarity with IEEE 1149.1, IEEE 1149.6, IEEE 1500, and IEEE 1687 standards. Experience supporting manufacturing test, yield analysis, and failure diagnostics.
• Prior experience leading geographically distributed DFT teams.

Pulled from the full job description

• 401(k)
• Health insurance
• 401(k) matching
• Paid time off
• Relocation assistance
• Life insurance
• Flexible schedule, * 401(k)
• 401(k) matching
• Flexible schedule
• Health insurance
• Life insurance
• Paid time off