System IP/RTL Design Engineer

• Work on RTL design of System IP blocks
• Work independently while closely collaborating with other designers as well as members of verification, physical design, performance and power teams
• Work on developing and maintaining Front-End Tools, Flows and Methodologies
• Work on creating scripts that automate repetitive daily tasks of team members Support Silicon bring-up activities

• Proficient in RTL design using Verilog and System Verilog
• Experienced in setting up and maintaining front-end tools for Synthesis, LEC, Lint and Low Power Analysis
• Excellent debug and problem-solving skills. Experienced in Silicon bring-up activities
• Experienced in timing and coverage closure
• Proficient with UNIX/Linux and programming languages such as PERL, Python, TCL, and Unix Shell Scripting
• Prior experience of having worked with interconnects, caches and/or cache coherency would be an added advantage

Preferred candidate will possess the following:

• Verilog/System Verilog
• GIT
• Perl
• Python
• Tcl/Tk
• C/C++
• Jenkins, Jira