DFT Design Engineer

Intel Corporation
Fort Collins, CO, United States
about 1 month ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Starter
Experience required
6 years minimum
Compensation
$106,000.0 - $149,000.0
Working hours
Regular working hours

Tech stack

Artificial Intelligence Cloud Computing Code Coverage Computer Programming Computer Engineering Data Centers Software Debugging Perl (Programming Language) Intacct Python (Programming Language) QuickBooks (Software) Software Deployment
+4 more
Tcl (Programming Language) Web Services High Performance Computing Information Technology

Job description

As a DFT Design Engineer, you will play a vital role in shaping the quality and performance of Intel’s silicon products. You will contribute to the development of cutting-edge technologies by designing and verifying robust Design for Test (DFT) features that ensure manufacturability and reliability. Your work will directly impact Intel’s ability to deliver high-quality products to market quickly, meeting both performance and quality objectives. This position offers the opportunity to collaborate with cross-functional teams, influence design methodologies, and drive innovation in test strategies for SoC and functional IP blocks., * Develop logic design, register transfer level (RTL) coding, and implement DFT architectures including SCAN, MBIST, BSCAN, and TAP.

  • Collaborate in the definition of architecture and microarchitecture features for DFT blocks and subsystems.
  • Optimize logic to achieve power, performance, area, timing, test coverage, and defect per million (DPM) goals.
  • Write and generate RTL and structural code for DFT integration, ensuring design integrity for physical implementation.
  • Review and execute verification plans to ensure design features meet architecture specifications.
  • Resolve RTL test failures and implement corrective measures to ensure feature correctness.
  • Support SoC customers for successful integration of DFT blocks, contributing to high-quality IP and SoC designs.
  • Develop high-volume manufacturing (HVM) test content for rapid bring-up and production deployment on automatic test equipment (ATE).
  • Collaborate with post-silicon and manufacturing teams to verify features in silicon and support debugging requirements., Architect and implement enterprise GenAI platforms (RAG and agentic systems), design knowledge retrieval, orchestration, tool-using agents and human-in-the-loop workflows, ensure production readiness and governance with product/data/security teams, define platform engineering best practices, and solve complex platform challenges with broad autonomy. Top Skills: Agentic SystemsApi DesignGenaiGenerative AiHuman-In-The-Loop WorkflowsKnowledge RetrievalObservabilityOrchestrationPlatform EngineeringRetrieval Augmented Generation (Rag)Tool-Using Agents Wipfli

Manager, Financial Reporting - Nonprofit Clients

2 Hours Ago Remote or Hybrid United States 97K-145K Annually Mid level 97K-145K Annually Mid level Cloud * Fintech * Software * Business Intelligence * Consulting * Financial Services Manage financial reporting for nonprofit clients, assisting with budgeting, forecasting, and improving processes. Coach staff and enhance technology integration. Top Skills: Quickbooks OnlineSage Intacct Wipfli

Requirements

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. This is an entry level position and will be compensated accordingly. Intel’s sponsorship guidelines: Learn more Link: Intel Careers, * Bachelor’s degree in computer or electrical engineering, or a related field with no prior experience required.

  • 6+ months of experience with design tools
  • 6+ months with RTL coding and DFT techniques., * Master’s in computer engineering or computer science with 6+ months of experience
  • Familiarity with test architecture including SCAN, MBIST, BSCAN, and TAP.
  • Familiarity with RTL coding, DFT techniques, and timing closure methods.
  • Experience with design tools and methodologies such as ATPG and coverage analysis.
  • Experience configuring EDT setups and resolving stuck-at and at-speed test scenarios.
  • Proficient programming skills in TCL, Python, Perl, and/or C++.
  • Knowledge of GLS for test scenario resolution and ATPG coverage analysis
  • Strong communication and collaboration skills, with a focus on teamwork across diverse engineering groups.

Benefits & conditions

Posted Yesterday Be an Early Applicant In-Office Fort Collins, CO, USA 106K-149K Annually Entry level In-Office Fort Collins, CO, USA 106K-149K Annually Entry level Design and verify DFT features for SoC and IP blocks, develop RTL and structural code, implement SCAN/MBIST/BSCAN/TAP, optimize for power/performance/area/timing/test coverage, create verification plans, resolve RTL test failures, support SoC integration, develop HVM test content for ATE, and collaborate with post-silicon and manufacturing teams for silicon debug., We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD, Remote or Hybrid Denver, CO, USA 122K-165K Annually Mid level 122K-165K Annually Mid level Cloud * Fintech * Software * Business Intelligence * Consulting * Financial Services This role involves managing accounting advisory services for manufacturing clients, including financial reporting, process improvement recommendations, and team leadership. Top Skills: FishbowlKatanaMS OfficeNetSuiteQuickbooks Online

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