Senior FPGA Engineer

• Define microarchitecture with cross-functional teams
• RTL design, synthesis, and timing closure
• Verification planning and simulation (SystemVerilog)
• Develop and validate FPGA lab platforms

• Strong FPGA design experience in high-speed networking (100Gbps+)
• Experience with PCIe, RDMA, CXL, NVLink or similar
• Proficient in SystemVerilog/Verilog/VHDL
• Experience with FPGA tools (Vivado, Quartus, Vitis)
• Scripting skills (TCL, Python)
• Embedded systems and host interface experience

Bonus Skills

• Experience with advanced FPGA platforms (Versal, Agilex)
• Exposure to HPC or data centre systems