Senior FPGA Engineer

Platform Recruitment
Cambridge, UK
about 1 month ago

Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Experience required
7 years minimum
Working hours
Regular working hours

Tech stack

C++ (Programming Language) Code Review DevOps Ethernet Firmware Field-Programmable Gate Array (FPGA) Hardware Design Python (Programming Language) PCI Express Static Timing Analysis SystemVerilog Vivado
+4 more
High Performance Computing Hardware Testing Low Latency Real Time Data

Job description

Senior FPGA Engineer - Cambridge - £80k-£130k Platform Recruitment has partnered with a cutting-edge technology firm developing ultra-low-latency FPGA platforms that power some of the fastest systems in the world. This is an opportunity to work at the sharp end of hardware design; where every nanosecond counts - joining a team that builds high-performance, globally deployed solutions. The Role As a Senior FPGA Engineer, you’ll take technical ownership of complex digital designs: from concept through to verification and hardware validation. You’ll architect new FPGA platforms, optimise latency and throughput, and collaborate with software and DevOps teams to deliver end-to-end solutions that push the boundaries of performance. What You’ll Be Doing Architecting and implementing RTL designs on high-end FPGAs (Xilinx / Intel). Performing simulation, synthesis, P&R, and timing analysis for ultra-low-latency systems. Leading the definition of micro-architectures and verification

Requirements

environments. Driving technical excellence across the FPGA team through mentorship and code reviews. Collaborating with firmware, software and infrastructure teams to optimise full-stack performance. What You’ll Need 7+ years’ FPGA / RTL design experience in timing-critical systems. Strong background in SystemVerilog, synthesis, timing closure and verification. Hands-on with Vivado / Quartus or equivalent toolchains. Familiarity with AXI, PCIe, Ethernet or custom high-speed interfaces. Nice to Have Exposure to high-performance computing, networking or real-time data systems. Knowledge of C/C++ or Python for tooling, verification or firmware collaboration. Appreciation for hardware-software co-design and system-level optimisation.

Apply for this position

This job is hosted externally. Click below to view the full posting and apply.

Apply on www.apply4u.co.uk

Good distractions

Talks and stories from around this role — technically off-topic, practically not.

2:17 min

Mapping the maturity roadmap for scaled devops adoption

Dominik Krichbaum Dominik Krichbaum · WWC Europe 2026

4:52 min

Connecting namespaces with local virtual ethernet pairs

Oliver Seitz Oliver Seitz · WWC 2025

4:18 min

Prioritizing communication and structural awareness over strict tool mastery

Liam Hurrel +1 · WWC 2021

3:18 min

Scaling global network engineering through DevOps culture

Stuart Clark · LIVE

1:20 min

Identifying multi-disciplinary talent for developer experience engineering roles

Hazal Mestci +1 · Coffee With Developers

2:12 min

Implementing automotive ethernet and connected remote vehicle telemetry applications

David Romić · WWC 2023

Videos

See all

Related articles

See all