ASIC / NoC Power and Solutions Senior/Staff Engineer - Qualcomm - Guyancourt, France

Experteer Overview In this role you contribute to deploying and supporting Qualcomm’s QITC NoC technology across multiple SoCs and product lines. You collaborate with architecture, hardware, software, verification, and post-silicon teams to ensure efficient use of interconnect and power features. You will help define interconnect requirements, resolve NoC power issues, and validate new power architectures. The work combines hands-on debugging with cross-functional training and technical leadership to scale QITC solutions globally. You will be at the core of powering SoCs with innovative NoC and power-management capabilities, shaping performance and cost at scale. Pay / Benefits * Collaborate with cross-functional teams to ensure effective use of QITC NoC technology in Qualcomm SoCs * Contribute to defining interconnect requirements and configuration for various SoCs * Provide support on power issues and NoC-related technology across QITC solutions * Help resolve NoC power micro-architecture and NoC power unit integration issues * Participate in defining and validating new or improved power architectures and NoC units * Develop technical materials and organize training for teams worldwide Tasks * Mastered or strong understanding of overall SoC development flow including architecture, RTL design, verification, and silicon bring-up * Knowledge of system-level features (memory mapping, MMUs, cache, QoS, security) * Experience with low-power techniques and resolving power-related issues * Strong analytical skills for debugging in simulation, emulation, or silicon * Familiarity with interconnect protocols (AHB/AXI/ACE/ACE-Lite/CHI) and NoC concepts * Ability to adapt quickly to changes and communicate effectively Key requirements *

ASIC and NoC power unit integration issues * Participate in defining and validating new or improved power architectures and NoC units * Develop technical materials and organize training for teams worldwide Tasks * Mastered or strong understanding of overall SoC development flow including architecture, RTL design, verification, and silicon bring-up * Knowledge of system-level features (memory mapping, MMUs, cache, QoS, security) * Experience with low-power techniques and resolving power-related issues * Strong analytical skills for debugging in simulation, emulation, or silicon * Familiarity with interconnect protocols (AHB/AXI/ACE/ACE-Lite/CHI) and NoC concepts * Ability to adapt quickly to changes and communicate effectively Key requirements *