PLL Design Engineer

Experteer Overview As an experienced Circuit Design Engineer you’ll define, specify and implement advanced PLL IPs powering AMD products. You will work within a fast-growing PLL design team, contributing to mixed-signal circuits in FinFET technology and guiding design from architecture to tape-out. You’ll collaborate across mask design and post-silicon characterization to ensure high-quality silicon. This role offers impact in next-gen HPC, AI, and cloud solutions, with opportunities to mentor peers and shape future PLL technology. Compensation / Benefits * Design complex building blocks of a PLL including architecture development and transistor-level circuit design * Run pre-tapeout verification flows to confirm performance, power, reliability and timing * Collaborate with mask design engineers to deliver physical design and define production/test plans with post-silicon teams * Lead/mentor junior engineers Tasks * Solid knowledge of mixed-signal circuit design in FinFET tech, especially PLLs and subblocks (VCO, charge-pump, dividers, LDO, bandgap, TDC, interpolator, high-speed buffers) * Strong tool proficiency for analog design and physical design activities * Experience with simulation and verification tools (Spectre, HSPICE, MATLAB, SystemVerilog, Python, Perl) * Familiarity with Cadence ADE-L and ADE-XL; Monte Carlo, noise, aging, EM and IR drop analyses; Calibre/ICV for DRC/LVS * Proven ability to work in a team with good interpersonal skills; strong analytical/problem-solving and attention to detail * Self-starter capable of driving tasks to completion Key requirements *

Experteer Overview As an experienced Circuit Design Engineer you’ll define, specify and implement advanced PLL IPs powering AMD products. You will work within a fast-growing PLL design team, contributing to mixed-signal circuits in FinFET technology and guiding design from architecture to tape-out. You’ll collaborate across mask design and post-silicon characterization to ensure high-quality silicon. This role offers impact in next-gen HPC, AI, and cloud solutions, with opportunities to mentor peers and shape future PLL technology. Compensation / Benefits * Design complex building blocks of a PLL including architecture development and transistor-level circuit design * Run pre-tapeout verification flows to confirm performance, power, reliability and timing * Collaborate with mask design engineers to deliver physical design and define production/test plans with post-silicon teams * Lead/mentor junior engineers Tasks * Solid knowledge of mixed-signal circuit design in FinFET tech, aaaaa plans PLLs and subblocks (VCO, charge-pump, dividers, LDO, bandgap, TDC, interpolator, high-speed buffers) * Strong tool proficiency for analog design and physical design activities * Experience with simulation and verification tools (Spectre, HSPICE, MATLAB, SystemVerilog, Python, Perl) * Familiarity with Cadence ADE-L and ADE-XL; Monte Carlo, noise, aging, EM and IR drop analyses; Calibre/ICV for DRC/LVS * Proven ability to work in a team with good interpersonal skills; strong analytical/problem-solving and attention to detail * Self-starter capable of driving tasks to completion Key requirements *