DFT Engineer, Google Cloud

Google LLC
Sunnyvale, CA, United States
7 days ago
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Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Experienced
Experience required
3 years minimum
Working hours
Regular working hours

Tech stack

Artificial Intelligence Code Coverage Software Debugging Joint Test Action (IEEE Standards) Google Cloud System-level Testing Physical Design

Job description

Experteer Overview In this role you will shape DFT strategies for Google’s AI/ML hardware, including TPUs, to ensure high test quality and scalable silicon. You’ll define and implement DFT architectures, integrate MBIST and JTAG/IP blocks, and verify test logic across complex SoCs. You will collaborate with Design and Physical Design teams to enable robust, testable silicon at scale. This is a chance to influence the reliability of AI accelerators used by billions of users. Compensation / Benefits * Define and implement DFT architectures and flows (Scan, MBIST, JTAG/iJTAG) for complex SoCs * Integrate DFT IP (test controllers, TAP, MBIST, eFuse logic) and connect to core and TAP interfaces * Verify test logic, generate test patterns, and address test coverage issues * Collaborate with Design and Physical Design teams to enable Test Access Port and testability in hardware * Develop System Level Test strategies and ensure compatibility with industry-standard methodologies (ATE, SLT) * Support debugging and validation of DFT implementations across RTL and physical design stages * Contribute to design verification and debugging of DFT components and test patterns * Evaluate and integrate DFT tooling and flows within the broader verification ecosystem Tasks * 3 years of experience in DFT architecture, implementation, ATPG, and verification for SoCs * Experience with ATE, MBIST, JTAG, or SLT * Knowledge of DFT flows, including scan, MBIST, and iJTAG Key requirements * equity * bonus target (15%) * benefits

Requirements

Support debugging and validation of DFT implementations across RTL and physical design stages * Contribute to design verification and debugging of DFT components and test patterns * Evaluate and integrate DFT tooling and flows within the broader verification ecosystem Tasks * 3 years of experience in DFT architecture, implementation, ATPG, and verification for SoCs * Experience with ATE, MBIST, JTAG, or SLT * Knowledge of DFT flows, including scan, MBIST, and iJTAG Key requirements * equity * bonus target (15%) * benefits

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