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FPGA Engineer (SystemVerilog)

Vivid Resourcing
Barcelona, Spain
7 days ago
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Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Compensation
€83,000.0 - €165,000.0
Working hours
Regular working hours
Job source
www.jobleads.com

Tech stack

Field-Programmable Gate Array (FPGA) SystemVerilog Verilog

Requirements

The right candidate has deep FPGA experience, strong Verilog/SystemVerilog design skills, and a solid grasp of CDC, timing, and verification.

About the company

Vivid Resourcing seeks a senior freelance FPGA Development Engineer in Barcelona to design and implement SystemVerilog FPGA functionality for synchronization and instrumentation platforms. This hands-on role focuses on multi-FPGA systems rather than ASIC design, working with a global R&D team.

Apply for this position

This job is hosted externally. Click below to view the full posting and apply.

Apply on www.jobleads.com
Prepare application

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