IO and Memory Sub-Sytem Architecture Organization

As a Senior Principal Architect of Memory & IO Sub-system, you’ll play a pivotal role in leading the architecture, design, and development of next generation of DRAM sub-system solutions for server and high-performance computing applications. In this full-time role, you’ll report directly to our VP of Engineering. Our Memory Interface Division is dedicated to developing all products related to Server and Client Memory Modules, and your contributions will be instrumental in developing solutions DDR6/LPDDR6/HBM solutions for Server and Client systems.

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities:

Lechnical Leadership

• Lead the architecture, design, and development of next generation of memory subsystem solutions.

• Drive technical decisions related to memory interfaces, PHY architecture, signal & power integrity, and system integration.

• Define subsystem requirements and translate system-level needs into architecture and design specifications.

• Provide technical leadership across multidisciplinary teams including ASIC, PHY, firmware, validation, system architecture, and platform engineering.

Memory Subsystem Development

• Develop expertise-driven solutions involving:

• DDR4/5/6, LPDDR4/5/6, HBM3/4/5 DRAM

• DDR4/5/6 Registered Clock Driver (RCD)

• DDR4/5/6 Data Buffer (DB)

• DDR4/5/6 DIMMs (RDIMM/LRDIMM/MRDIMM)

• DDR4/5/6 Server Platforms

• Analyze memory subsystem performance, timing, power, and interoperability requirements.

• Drive systems bring-up, debug, characterization, and performance optimization activities.

PHY Architecture and Design

• Define and review high-speed PHY architectures for next-generation memory and interface products.

• Develop and optimize:

• Transmitter (Tx) architectures

• Receiver (Rx) architectures

• Clocking and timing circuits

• Equalization schemes including DFE, CTLE, and related signal-conditioning techniques

• Evaluate signal integrity challenges and develop solutions to improve channel performance and margin.

Digital Design and Verification

• Contribute to digital design, architecture reviews, and RTL implementation strategies.

• Define verification methodologies and coverage requirements.

• Lead debugging and root-cause analysis of complex design and system-level issues.

• Collaborate with validation teams to ensure robust product functionality and compliance.

Specification and Customer Engagement

• Develop and maintain architecture specifications, design requirements, and technical documentation.

• Present technical proposals, design reviews, and architecture recommendations to engineering leadership, customers, and ecosystem partners.

• Translate JEDEC and industry standards into product requirements and implementation guidelines.

• Participate in customer discussions, technical reviews, and interoperability initiatives.

• Master’s Degree (M.S.) in Electrical Engineering, Computer Engineering, or a related technical discipline.

Experience

• 12+ years of industry experience in semiconductor, ASIC, memory, or high-speed interface development.

• Demonstrated experience leading complex technical projects and influencing architectural decisions.

Key Competencies

• System Architecture Leadership

• DDR5/DDR6/LPDDR5/HBM Memory Expertise

• High-Speed PHY Design

• Tx/Rx Circuit Architecture

• DFE/CTLE Equalization Techniques

• I2C, I3C, USB Interfaces

• Digital Design & Verification

• Technical Specification Development

• Analytical Problem Solving

• Executive-Level Presentations, ASIC (Application Specific Integrated Circuit), Analysis Skills, Architectural Design, Architectural Services, Artificial Intelligence (AI), Computer Engineering, Computer Firmware, Cross-Functional, DRAM, Debugging Skills, Design Verification, Ecosystems, Electrical Engineering, Equalization, Genetics, Graphic Design, I2C, IP (Internet Protocol), Industry Standards, Interoperability, Interoperability Requirements, Joint Electron Device Engineering Council (JEDEC), Leadership, Memory Hardware, Memory Subsystem, Network Operations Center, PHY, Performance Analysis, Performance Management, Performance Tuning/Optimization, Problem Solving Skills, Product Development, RTL Design, Receivers, Requirements Management, Root Cause Analysis, Semiconductors, Signal Integrity, System Architecture, System Integration (SI), Systems Analysis, Technical Leadership, Technical Presentation, Technical Writing, Technical/Engineering Design, USB

Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.

The US salary range for this full-time position is $180,000 to $334,200. Our salary ranges are determined by role, level and location. The successful candidate’s starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.

At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members have equitable access to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do our best work., undefined: Rambus Rambus was voted one of the Bay Area’s Top Workplaces based on surveys completed by employees. Workplace Dynamics compiles the list based purely on employee’s opinion of their employers. Over 4,000 organizations across America participated in the program.

Rambus is looking for talented, energetic people to join our team! We are committed to attracting, developing and motivating individuals who have the drive, passion, and determination to help us succeed. We offer an exciting work environment and a competitive compensation and benefits package. To join our team please submit your resume.

We maintain a searchable database, so you only need to submit your resume once. You will be considered for all relevant positions. We are an equal opportunity employer.

Notice to staffing agencies: Rambus Inc. does not accept unsolicited resumes from recruitment agencies. Accordingly, agencies are requested not to submit such resumes to our job postings, our employees, or any other part of our company. Recruitment agencies that nonetheless submit unsolicited resumes to Rambus Inc. agree and acknowledge that the company is free to use them at its discretion, including without limitation directly contacting the candidate, and will not under any circumstances be responsible for any recruitment or similar fees related to such unsolicited resumes.

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Senior Principal Engineer to join our MIC team in San Jose, CA. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer., Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.