Senior Digital Verification Engineer

IC Resources
Bregenz, Austria
19 days ago
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Role details

Contract type
Permanent contract
Employment type
Full-time (> 32 hours)
Experience level
Expert
Experience required
5 years minimum
Working hours
Regular working hours
Job source

Tech stack

Computer-Aided Design Code Coverage Digital Arts Formal Verification Specman SystemVerilog

Job description

As a Senior Digital Verification Engineer, you will play a critical role in ensuring the functional correctness and quality of complex digital designs. Your key responsibilities will include:

  • Leading the development of UVM-based verification environments
  • Performing pre-silicon verification of digital and mixed-signal designs
  • Creating detailed verification plans in collaboration with design and systems teams
  • Implementing automated checks and maintaining spec-to-coverage traceability
  • Defining and driving functional and code coverage closure
  • Providing regular verification progress updates to stakeholders
  • Collaborating with design and systems teams to resolve bugs
  • Tracking bugs, functional coverage, and RTL code coverage
  • Mentoring junior team members and driving continuous improvements in verification processes and tools

Requirements

Are you passionate about cutting-edge technologies and future-oriented projects in semiconductor design? We are seeking a highly skilled and motivated Senior Digital Verification Engineer to join our dynamic team. As a market leader in turnkey solutions, we work on a diverse range of products across Automotive, Compute, Industrial, Medical, and other markets. This role offers an exciting opportunity to contribute to innovative projects in a collaborative and supportive environment, with ample opportunities for professional growth., * Bachelor’s or Master’s degree (or equivalent) in Electrical Engineering or Physics

  • A minimum of 5 years of professional experience in Digital Verification

Technical Skills

  • Expertise in advanced verification methodologies, particularly UVM
  • Proven experience in designing and implementing testbench architectures
  • Strong proficiency with verification languages such as SystemVerilog, Specman, or ‘e’
  • Familiarity with industry-standard CAD tools and verification flows

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