Digital Verification Engineer

1. Verification Environment Ownership * Own the testbench: Design, build, and maintain the verification environments for our digital subsystems - from block level through full-chip / subsystem integration - for both FPGA and ASIC targets. * Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches. * Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically.

2. Test Development & Coverage * Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior. * Coverage-driven closure: Define functional and code-coverage goals and drive them to closure - identifying coverage holes and writing the stimulus to fill them. * Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur.

3. Simulation, Debug & Regression * Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix. * Regression: Stand up and maintain automated regression suites - keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change. * Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design-debug loop.

4. System Bring-up & HW/SW Co-validation * Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware. * Software collaboration: Partner with firmware / software engineers during system bring-up - validating register maps, interfaces, and boot / init sequences across the HW/SW boundary. * Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions.

• Experience: 3-7 years of digital verification experience on FPGA or ASIC designs.
• Language: Proficiency in Verilog (SystemVerilog strongly preferred).
• Tools: Hands-on experience with logic simulators - Modelsim / Questasim and/or NC-Verilog.
• Methodology: Solid grounding in logic-simulation and verification fundamentals - testbench construction, constrained-random stimulus, functional / code coverage, and assertions.
• Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field.

Strong Pluses

• Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols).
• Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation.
• Structured verification methodology experience (UVM or equivalent).
• Familiarity with networking / switching datapaths or high-speed interfaces.

• Zero Functional Escapes: The blocks you verify reach silicon and the field free of functional bugs, because your environment exercised the corner cases before anyone else could hit them.
• Coverage You Can Defend: Every milestone is cleared with documented functional and code coverage - no block signs off on “it seems to work.”
• A Regression the Team Trusts: Fast, deterministic regressions catch breakage the same day it’s introduced, so designers refactor with confidence.
• Bring-up Without Surprises: Because pre-silicon simulation matched real behavior, lab bring-up and HW/SW integration go smoothly - no late-stage firefighting.

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