IP, EDA and Ecosystem Manager

• No endless meetings, no PowerPoint presentations to convince middle management., TylSemi is looking for a IP, EDA and Ecosystem Manager who can sit at the intersection of silicon, ecosystem, and customer success. You will own the operational thread that connects our stretagic initiatives to customers and semiconductor ecosystem - making sure every engagement moves with precision from idea to silicon.

This is a high-visibility, high-ownership role at a company in its earliest and most consequential stage. You will work directly with founders, customers, the leading semiconductor ecosystem players. No layers, no ambiguity about impact.

What you’ll do

• Manage all active customer engagements end-to-end: from architectural spec alignment through tape-out, KGD testing, packaging, and volume shipment milestones
• Ensure alignment with ecosystem partners - including foundries, OSAT/packaging houses, EDA vendors (Synopsys, Cadence), and IP partners
• Translate customer requirements (silicon architecture, interface specs, package form factor, delivery schedules) into internal program plans with clear owners and dates
• Build and maintain program trackers, risk registers, and executive dashboards covering each engagement
• Drive gate reviews and weekly program syncs across internal RTL/DV, physical design, and validation teams
• Manage internal and external scoping and delivery timelines in coordination with technical and business teams
• Identify and escalate risks early; propose and implement mitigations before they become schedule threats

If you’re reading this, you’re probably comfortable. You have a good job at a stable company with all the benefits., * 15+ years of technical ecosystem management experience in semiconductor, custom silicon, or chiplet/advanced packaging environments

• Direct experience interfacing with ecosystem partners - chip development schedules, interdepencies on EDA and IP, tape-out schedules and silicon bringup timelines
• Familiarity with silicon fabrication, advanced packaging formats: CoWoS, InFO, 2.5D/3D integration, substrate/interposer-based assembly
• Technical fluency in SoC or chiplet design flows - enough to understand RTL milestones, DV sign-off, PD handoffs, and silicon bring-up phases without needing translation
• Strong communication skills - comfortable presenting program status and risk posture to internal and external stakeholders
• Proficiency with program tracking tools (and spreadsheet-based trackers); experience building program infrastructure from scratch is a plus
• Familiarity with key connectivity IPs UCIe, PCIe Gen 5/6/7+, or high-bandwidth D2D interconnect standards is a strong plus

Nice to Have to Shine

• Prior experience at a chiplet startup, merchant silicon company, or systems company
• Background in AI/ML infrastructure silicon - accelerators, network switches, CPO-enabled platforms
• Familiarity with IVR/PMIC integration challenges in advanced packaging
• Exposure to EDA infrastructure programs (SNPS/CDNS cloud flows)

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That’s what we solve. TylSemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.