FPGA Engineer
Eu Recruit
27 days ago
Role details
Contract type
Permanent contract Employment type
Full-time (> 32 hours) Working hours
Regular working hours Languages
English Experience level
JuniorJob location
Tech stack
Firmware
Field-Programmable Gate Array (FPGA)
Python
Quantum Computing
Reduced Instruction Set Computing
Static Timing Analysis
SystemVerilog
Verilog
VHDL
Vivado
Digital Access Carrier System
Yocto
Job description
- Design and implement SystemVerilog/Verilog modules for advanced quantum control systems, including:
- Real-time distributed signal acquisition and generation using high-speed ADCs and DACs
- Integration of high-speed vision interfaces such as CameraLink, CoaXPress, DisplayPort, or HDMI
- Development of comprehensive testbenches and simulation frameworks in SystemVerilog/Verilog and/or Python (cocotb)
- Co-design of memory-mapped firmware and software for PS-PL interfaces on SoCs
- Design of robust clocking and trigger architectures for synchronized, multi-board systems
Requirements
- 3+ years of FPGA development experience (or 1+ year with a Master's degree)
- Bachelor's or Master's degree in Electrical Engineering or a related discipline
- Strong proficiency in synthesizable SystemVerilog, Verilog, or VHDL and functional verification
- Experience achieving timing closure and performing static timing analysis across multiple high-speed clock domains
- Prior experience in signal or image processing, or control systems engineering
- Deep understanding of ARM AXI4, AXI-Stream, and AXI-Lite bus protocols
- Experience developing firmware for SoCs using ARM, RISC-V, or PC400 architectures
- Ability to collaborate effectively with experimental physicists and engineers in an interdisciplinary environment
Preferred / Additional Skills
- Experience working with high-bandwidth ADC/DACs (>1 GSPS)
- Familiarity with high-speed camera acquisition and in-memory image processing
- Hands-on experience with Xilinx SoC devices and tools such as Vivado and Vitis/SDK
- Knowledge of embedded OS and BSP generation using Yocto or PetaLinux