Principal EDA SW Engineer
Analog Devices
1 month ago
Role details
Contract type
Permanent contract Employment type
Full-time (> 32 hours) Working hours
Regular working hours Languages
English Experience level
SeniorJob location
Tech stack
Artificial Intelligence
Software Applications
C++
Computer Programming
Computer Engineering
Data Structures
Linux
Electronic Design Automation
Python
Systems Development Life Cycle
Software Engineering
Information Technology
Modeling and Simulation
Software Version Control
Job description
We are looking for a highly skilled and motivated Staff EDA Software Development Engineer to help SVV build industry-leading, best-in-class DV solutions. The EDA SW Development Engineer will research, develop, apply, and support application software for Design Verification and Virtual Test/Eval, as part of ADI's shift-left initiatives., * Architect and implement EDA SW for the automation of Design Verification (DV) and Virtual Test/Evaluation of complex IC/system products
- Gather requirements, drive consensus and collaborate across a cross-functional, multi-discipline team & stakeholders
- Develop modeling and simulation methodology of Virtual Test/Evaluation of ICs to leverage Design Verification (DV) collaterals
- Identify areas of significant competitive advantage and execute through EDA solution development
- Apply AI/ML methods to create superior solutions to design automation problems
- Expertise with CI/CD pipelines, automated build and test processes, and integration with version control systems.
- Represent the organization in internal and external technical forums, sharing best practices and driving innovation in engineering enablement.
- Champion the adoption of new technologies and methodologies, evaluating emerging tools and guiding their integration into standard practice. All projects are expected to have a significant EDA software component with the expectation to contribute to all aspects of the software life cycle including idea conception, product definition, software development, maintenance, and user support. By working closely with industry-leading DV methodology and practitioners, collaborating with external researchers, and interfacing with commercial EDA tools, your work will provide leading-edge, targeted differentiation of design automation methods for ADI's new product development teams. Success is measured by the impact on IC/System development projects that produce great products for the customers of Analog Devices. The ideal candidate will have a sound understanding of DV tools and methods, concepts, and design automation algorithms with a passion for enterprise software development.
Requirements
- Bachelor's/Master's/Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science, with 10+ years of relevant experience building EDA simulation tools (digital and/or analog mixed-signal)
- Excellent C/C++ programming skills
- Proficiency designing data structures, algorithms, and software engineering principles
- Industry experience developing and maintaining C++ based applications on a Linux environment
- Deep expertise in EDA (Electronic Design Automation) algorithms
- Strong automation skills using languages like Python
- Understanding of Design Verification EDA tools & methods, as well as Digital, Analog/Mixed-Signal simulation preferred
- Experience with applying AI/ML technology to EDA preferred
- Strong communication skills, with the ability to clearly convey technical details
About the company
Analog Devices, Inc. (NASDAQ: ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible . Learn more at and on and., The Engineering Enablement group provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Systems Verification and Validation (SVV) team within the Engineering Enablement organization in the CTO Office. SVV is responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire DV landscape - including Unified Metric-Driven Verification (MDV), SystemVerilog (SV)/UVM-based methods, Mixed-Signal DV, Post-Silicon Validation Shift-Left, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies.