Senior Engineer, Design Verification Engineering
Role details
Job location
Tech stack
Job description
The Edinburgh team is seeking a Senior Design Verification Engineer to grow its talented group located in the city centre of the Scottish capital. ADI's Personal Electronics Solutions Group has been leading the industry, working with the world's leading consumer companies, providing high value audio solutions for the portable, wearable, and gaming markets. We are poised for significant growth as we enter the next phase, driven by the insatiable consumer demand for new technologies and access to information., * Complete verification ownership - Testbench Architecture, Testplan and Testbench Development, Functional Coverage Closure and Code Coverage Closure
- Verification of key digital IP blocks in differentiated mixed-signal devices targeted for the consumer market
- Debug efficiently while clearly articulating gating issues to engineering leads
- Successful Integration of block level testbenches at SoC top-level and verifying proper SoC integration
- Usage of industry standard methodologies like UVM and constrained random to achieve verification goals
- Actively explore and deploy techniques to improve coverage while reducing verification time
- Involvement in post-silicon activities such as silicon bring-up, evaluation support, and ATE pattern bring-up
- Continue to improve DV methodologies consistent with the group's wider business objectives, * We allow our employees the freedom to explore new ideas and the autonomy to determine how to best achieve goals
- We place great value on individual judgment
- We emphasize professional development and mentoring
- Above all, we recognize that our employees' personal goals and the company's goals are closely related and must support each other, * Complete verification ownership - Testbench Architecture, Testplan and Testbench Development, Functional Coverage Closure and Code Coverage Closure
- Verification of key digital IP blocks in differentiated mixed-signal devices targeted for the consumer market
- Debug efficiently while clearly articulating gating issues to engineering leads
- Successful Integration of block level testbenches at SoC top-level and verifying proper SoC integration
- Usage of industry standard methodologies like UVM and constrained random to achieve verification goals
- Actively explore and deploy techniques to improve coverage while reducing verification time
- Involvement in post-silicon activities such as silicon bring-up, evaluation support, and ATE pattern bring-up
- Continue to improve DV methodologies consistent with the group's wider business objective
Requirements
Closure, It, Verilog, Communication Skills, Perl, Utilities, Formal Verification, Scripting Languages, Systemverilog, Python, Digital Signal Processing, The successful candidate will join a diverse team that is motivated, supportive, and eager to share its knowledge. It is the ideal place to enhance both technical expertise and interpersonal skills, whilst collaborating with our design teams worldwide., * Electronic Engineering/Computer Engineering degree with 5-8 years of progressive experience in digital design and verification
- Demonstrated experience in developing UVM-based testbench infrastructure, functional cover point development, code coverage analysis/closure, and assertion development
- Strong understanding and experience of Verilog and SystemVerilog
- Proficiency in Scripting languages and utilities including Makefile, Python, Perl etc.
- Experience with both IP and SoC level verification
- Strong inter-personal, teamwork, and communication skills are required, * Knowledge in AHB/AXI/APB protocols, knowledge in Audio Interface would be a plus
- Ability to create a verification plan with work breakdown and drive it independently as a (sub)project
- Experience in Power aware simulations or Formal Verification
- Experience in Audio IP and SoC level verification
- Understanding of DSP (Digital Signal processing) concepts
- Passion for Audio
- Proactive and growth mindset
