Network Architecture Senior Engineeer

As SoC Interconnect Senior Architect, you will work with a team of engineers to develop and verify state-of-the-art Memory Interface and Network-on-Chip IP cores. You will be working on advanced device architectures, design definition, implementation, and verification. You will also be developing design examples and simulation models, accompanied by a rich set of technical documentation.

In this team your responsibility will include, but not limited, to:

• Actively work with SoC Architecture, verification, physical design team, Soc Floorplan, core teams to achieve system targets for performances, area and power.
• Coherent and non-coherent interconnects within the chip, coherency protocol, directory structure, bandwidth, and latency targets.
• Evaluate new IPs, driving new protocol deployments as well as defining system wide guidelines for IPs to inter-operate together in the SoC.
• Deliver RTL to the SoC team, support verification and silicon validation teams, and work with SW teams to support successful deployments of the interconnects.

·7+ years of solid experience in IP/SoC design.

·Working knowledge of System on Chip and Network on Chip Architectures.

·General knowledge of on-chip network protocols: AMBA, AXI, CHI, ACE or APB.

·General knowledge of cache coherent memory systems and interconnect.

·Familiarity with RISC-V architecture.

·Working Knowledge with SystemVerilog or Verilog, C or C++, scripting languages such as Python

·Hands-on experience with SoC Design, Verilog RTL coding and simulation software.

·General knowledge of functional and performance simulators.

·Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification. Soft Skills, We are looking for team players that focus on the outcome of the team above the individual needs, with respect and honest challenge. Individuals are encouraged to work well with the team. You have good communication and enjoy working with your teammates, having fun at the same time that you strive to do your best to provide unique products for our customers.

We are looking for outstanding people willing to join our mission to change this industry and help to build a better world.

If you feel identified with Openchip, please contact us. We can offer a competitive compensation package in a flexible work schema that will help you to keep a balance between your personal and professional life.

At Openchip & Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential - regardless of race, gender, ethnicity, sexual orientation, or gender identity. #J-18808-Ljbffr

Openchip is a European Silicon Engineering Company, headquartered in Barcelona, Spain. We aim to democratize the usage of Chips by developing Systems on Chip, SOCs, that combines RISC-V and accelerated chiplets for AI and HPC, everything interconnected with UCIe open interfaces. Our technologies will provide a value in multiple fields as Artificial Intelligence, Security and Privacy and Carbon Footprint Reduction. We are willing to change the Silicon Industry and help to build a more sustainable world, where collaboration and openness are by default. Our chips will be used in High Performance Computing, Autonomous Driving, Telecommunications, Personalized Medicine, Edge Computing and Cloud. We are looking for outstanding people willing to join our mission to change this industry and help to build a better world. About the function The Network-on-chip Architecture team consists of a multi-disciplinary group involved from early product specification and analysis effort to final RTL delivery to the SoCs. One aspect of the process is to identify architecture bottlenecks and drive micro-architecture choices using performance and power analysis, and to provide the SoC team with design guidelines for bus protocol compliance and best power interconnect.