Digital Verification Lead Engineer

• Act as verification lead on projects
• Provide technical leadership & mentoring
• Prepare design verification plan based on design specifications
• Plan and schedule projects, assign and track tasks for team members
• Develop design verification methodologies and implement standard debug flows
• Participate in design reviews
• Maintain design verification environment and track & close design bugs
• Work with designers in verification and validation of circuit designs
• Utilize the latest techniques, tools, and technologies for design verification activities

• Excellent communication skills, strong team player
• Good scripting techniques, experience with regression setup & management
• Deep understanding of simulation and verification environments, including debugging techniques
• Experience with Gate Level Simulation flows and debug.
• Strong knowledge on Metrics-driven verification (incl. verification planning and coverage closure)
• Experienced with test bench development using the latest methodologies
• Experience with 3rd party VIP usage and test development (a plus)
• Experience with emulation platforms and/or FPGA prototyping (a plus)
• Experience with Assertion Based Verification (a plus), * 7+ years' experience in the semiconductor industry
• Experience in leading and managing a team across multiple sites
• Proven track record in verifying complex designs (preferably in high volume applications)
• Skilled in trade-offs between quality and schedule
• Experience in constrained random test bench development
• Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous
• Extensive digital verification background with some UVM experience
• Coordinate and oversee external sub-contractors to scale up verification workloads

Education Bachelor of Engineering in Electronics and Electrical Engineer (equivalent or higher)