Senior Digital Verification Engineer

We are seeking a highly skilled Digital Verification Engineer to join our team and contribute to the follow-up and oversight of the development and validation of next-generation SoC designs. This role is focused on functional verification at the RTL level, ensuring design correctness and compliance across complex high-speed and low-speed interfaces. It will involve little coding, so we are looking for Senior Engineers to oversee the activities and review coding., * Develop and execute functional verification plans for complex SoC subsystems.

• Follow up on and oversee verification activities throughout the development lifecycle
• Create and maintain verification environments , testbenches, and test cases
• Verify high-speed and low-speed interfaces (e.g., PCIe, Ethernet, DDR, AXI, I2C, SPI, UART, etc.)
• Analyze functional coverage, identify gaps, and drive closure
• Debug simulation failures and work with design teams to resolve issues
• Verify low-speed control/debug interfaces including SPI, JTAG, and SMBus.
• Validate integration of embedded microcontroller cores (ARC32 or RISC-V).
• Verify AXI-based system interconnects and bus protocols.
• Track functional and code coverage, driving verification closure.
• Collaborate closely with design and architecture teams to root-cause issues and ensure robust RTL sign-off.

• Solid background in Front-End (RTL-level) Functional Verification.
• Hands-on experience with SystemVerilog, UVM, assertions (SVA), and coverage-driven verification.
• Familiarity with protocol verification IP (VIP) for PCIe, CXL, AXI, or equivalent.
• Strong knowledge of high-speed and low-speed interface protocols.
• Experience verifying embedded processors or microcontrollers (RISC-V, ARC, or similar).
• Proven ability to debug complex design/verification issues.

Nice to Have

• Experience with performance verification and system-level test scenarios.
• Knowledge of verification acceleration/emulation flows.
• Familiarity with formal verification techniques.