ASIC Digital Design Verification Engineer, Sr Staff

Job Description: The selected candidate will serve as a technical leader within the Synopsys DesignWare Processor team, engaging in the development of cutting-edge DesignWare processor IP products. These products include HPC processors, NN accelerators, vision processors, and energy-efficient processors.

Responsibilities:

• Ownership & Accountability: Assume full responsibility for the quality of delivery for one or more verification function blocks within a product development effort.
• Plan & Spec Authorship: Author plans and specifications for owned functions.
• Guidance & Tracking: Guide, coach, and track team members to ensure appropriate execution of technical tasks.
• Escalation: Escalate overall team competencies as needed.
• Technical Work: Engage in architecture, micro-architecture, performance analysis, logic design, verification and validation, and related engineering flows or environments.
• Signoff Delivery: Manage necessary signoff delivery processes.
• Collaboration: Collaborate with cross-team or cross-site colleagues on various technical matters such as algorithms, methodologies, quality of delivery, SoC prototyping, and system bring-up.

• Education: Master's degree in Electrical Engineering (EE) or Computer Science (CS) from a reputed college.
• Experience: Minimum 10 years of experience in digital frontend design or verification for IP business.
• Leadership: Proven leadership and ownership experience with a solid track record of quality delivery and team capability escalation.
• Knowledge: Comprehensive knowledge in microprocessor architecture, memory architecture, and system architecture.
• Hands-On Experience:

• Architecture, micro-architecture, and RTL design.
• Functional and performance modeling, profiling, benchmarking, and simulation verification using UVM.
• Co-simulation, functional formal verification, functional coverage, regression flows/environments, and debugging.
• Authorship of technical specifications.

• Programming Skills: Proficiency in SystemVerilog, SystemVerilog Assertion, Verilog, C/C++, assembly, Perl, Python, and scripting languages.
• Tools: Experience with RTL linters, simulators, synthesizers, functional formal tools, functional coverage tools, team work tools (continuous integration, source control management, issue tracking), ADL-based generation tools (e.g., Synopsys ASIP Designer), and software toolchains.
• Multi-Site Development: Experience in multi-site development environments.
• Project Management Skills:

• Requirement profiling.
• Resource, work, and schedule planning and tracking.
• Risk and quality assessment and management.
• Justification of execution objectives, strategy, value proposition, and ROI evaluation.

• Communication Skills:

• Creation, modification, and review of documentation (design or verification work plans, engineering quality processes, test scenarios, test reports).
• Ability to profile values, requirements, issues, risks, and solutions for engineering works presentation.
• Persuasion and compromise skills for consensus building.
• Ability to follow disciplines for tracking issues and changes.

• Analytical Skills:

• Analysis of signoff requirements for product releases.
• Ability to analyze Quality of Results (QoR) and verification results for major milestone reviews and assessments.

• Team Player: Self-motivated, able to thrive in a fast-paced engineering environment.
• Leadership: Ability to guide, coach, motivate, and influence team members toward desired results.

This role demands a highly skilled and experienced professional who can lead technical teams, manage complex projects, and ensure the delivery of high-quality processor IP products. The candidate must possess strong analytical, communication, and leadership skills, with a deep understanding of digital design and verification processes.