Digital SoC expert designer - Technical leader (consultant)

Imec
6 days ago

Role details

Contract type
Temporary contract
Employment type
Full-time (> 32 hours)
Working hours
Regular working hours
Languages
English
Experience level
Senior

Job location

Remote

Tech stack

Logic Synthesis of Circuits
Field-Programmable Gate Array (FPGA)
Python
Matlab
Static Timing Analysis
Systems Architecture
Tcl (Programming Language)
Verilog
Scripting (Bash/Python/Go/Ruby)
Application Specific Integrated Circuits
GIT

Job description

  • Collaborate with system architect team, digital back-end team and embedded SW and validation as well as the other project stakeholders.
  • Lead RTL development for ASIC and FPGA. Supervise the verification planning and activities (possibly including mixed-signal projects).
  • Define and/or propose (new) way of working to maximize the efficiency of the design process.
  • Contribute to high-quality reports and documentation., We offer you an exciting temporary assignment in which you will be part of a community that makes the impossible possible. Together, we shape the technology that will define the society of tomorrow.

Requirements

  • MSc or PhD in electronics engineering with 10+ years of relevant experience in ASIC design.
  • Solid understanding of digital ASIC-design flow is required: logic synthesis, timing analysis, power estimation/simulation, logic equivalence, STA (DFT and/or P&R is preferred).
  • Structural way of working and ability to develop and manage activity planning is required.
  • Experience working closely with (internal or external) stakeholders is required.
  • Strong experience with digital circuit design in (System) Verilog is required. * Experience with SoC top level design and/or sub-systems is required; including low power techniques.
  • Experience with digital verification is preferred: plan definition, verification methodologies, code/functional coverage, constrained random verification, verification plan execution and tracking.
  • Knowledge of high-level synthesis methodologies is a plus.
  • Experience with Cadence IC design tools is preferred.
  • Knowledge of the FPGA-development flow is a plus.
  • Experience with scripting languages like TCL, Matlab and Python is required.
  • Experience with revisioning systems, like git is required.
  • Able to take initiative and responsibility for team's success. Thinking pro-actively, working independently and having a creative problem-solving attitude.
  • Have broad interest across disciplines and like to embrace new challenges.
  • Excellent communication skills in English (written and spoken).

About the company

We provide the flexibility to work both from our office premises and remotely from home. This to maintain a healthy work-life balance while being an integral part of our team. Please note that a 100% remote job is NOT possible, you need to be able to come onsite 3x/week in imec Leuven (Belgium).

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