Digital SoC Design Engineer
Imec
12 days ago
Role details
Contract type
Temporary contract Employment type
Full-time (> 32 hours) Working hours
Regular working hours Languages
English Experience level
SeniorJob location
Remote
Tech stack
Artificial Intelligence
Logic Synthesis of Circuits
Event-Driven Programming
Field-Programmable Gate Array (FPGA)
Python
Matlab
Multiprocessing
Static Timing Analysis
System on a Chip
Tcl (Programming Language)
Verilog
Scripting (Bash/Python/Go/Ruby)
Application Specific Integrated Circuits
GIT
Job description
- Making trade-offs for minimal power consumption at best performance and low cost, while considering scalability, maintainability and re-usability.
- Collaborate with digital back-end team for synthesis and physical implementation.
- Verification.
- Validate and characterize your own designs experimentally in a lab environment.
- Collaborate in an inter-disciplinary team.
- Understand (internal or external) customer needs, challenges and requirements and translate that into solutions that you can incorporate into your designs.
- Contribute to high-quality reports and documentation., We offer you an exciting temporary assignment in which you will be part of a community that makes the impossible possible. Together, we shape the technology that will define the society of tomorrow.
Requirements
- MSc or PhD in electronics engineering with 5+ years of relevant experience.
- Strong experience with digital circuit design in (System) Verilog is required.
- Following application experience is a preferred: Affiliation on hardware efficient AI accelerator, event driven computing, compute modalities like multi-core -processor systems, in memory computing, large data computing.
- Hardware modelling. Architecting and designing CPU and peripheral (sub-)systems.
- Experience with digital verification is preferred: verification plan definition and tracking, verification methodologies, code-functional coverage, constrained random verification.
- Understanding of the remaining steps of the digital ASIC-design flow is required: logic synthesis, timing analysis, power simulation, logic equivalence, DFT and-or P&R.
- Experience with scripting languages like TCL, Matlab and Python is required.
- Experience with revisioning systems, like git is required.
- Knowledge of FPGA-development is a plus.
- Knowledge of low-power designs is a plus.
- Experience with Cadence IC design tools is a plus.
- Experience with C and systemC is a plus. Structural way of working and ability to develop and manage activity planning is highly preferred.
- Previous experience working closely with (internal or external) stakeholders is a plus.
- Able to take initiative and responsibility for team's success.
- Thinking pro-actively, working independently and having a creative problem-solving attitude are attributes that define yourself.
- Have broad interest across disciplines and like to embrace new challenges.
- Excellent communication skills in English (written and spoken).
