Staff Hardware Architect

As a Senior Staff Hardware Architect, you will play a key role in defining, optimizing, and evolving cache coherency solutions within our advanced IP portfolio.

Your primary mission will be to design next-generation coherent interconnect architectures and ensure seamless integration with other Network-on-Chip (NoC) and System IP solutions, enabling efficient and coherent communication between processors, accelerators, and functional units.

You will work closely with hardware design, verification, and software teams, as well as with product management and commercial teams, to deliver high-performance, low-power, and highly reliable NoC solutions., Cache Coherency Architecture

• Provide expertise in evaluating industry-standard cache coherency protocols, as well as the proprietary protocol used in our highly configurable NoC IP
• Design complete, scalable, and robust cache coherency architectures aligned with overall SoC architectures
• Analyze customer requirements for complex coherent systems, including chiplet partitioning using die-to-die and chip-to-chip architectures based on standards such as:

• CHI C2C
• UAlink
• UCIe
• PCIe

• Define performance, power, and area (PPA) targets for configurable IP

NoC Integration

• Collaborate with SoC teams to ensure seamless integration of cache coherency within the overall architecture
• Optimize coherence architecture and microarchitecture within the NoC to reduce latency and increase bandwidth

Performance and Power Optimization

• Identify performance bottlenecks and power consumption issues
• Propose and implement innovative solutions to improve overall efficiency
• Work closely with hardware and software teams to verify and optimize coherence mechanisms

Protocol Verification

• Guide verification teams in defining verification strategies ensuring robustness and compliance of coherency protocols
• Support emulation teams during testing and debugging phases to validate coherence behavior under various functional and performance scenarios

Cross-Functional Collaboration

• Work with marketing and sales teams to gather customer requirements and market needs
• Collaborate closely with hardware design, software, and system architecture teams
• Provide technical expertise to Application Engineering teams to facilitate customer integration

Technology Monitoring and Innovation

• Maintain active technology watch on advances in cache coherency, NoC technologies, and die-to-die interfaces
• Evaluate new standards, methodologies, and industry trends and propose their integration into our IP.

Documentation and Communication Produce detailed technical documentation including architecture specifications, design guidelines, and white papers Communicate complex technical concepts clearly to both technical and non-technical stakeholders

• Engineering degree, Master's degree, or equivalent in electronics, computer engineering, or a related field
• Proven experience as a Cache Coherency Architect, SoC/NoC Architect, or advanced design engineer

Strong expertise in: *

• SoC and NoC architectures
• cache coherency protocols
• memory hierarchies

• Solid understanding of interactions between caches and NoC interconnects
• 8+ years of experience in verification and validation of coherent systems
• Knowledge of hardware description languages (HDL) and SoC design tools
• Excellent analytical, problem-solving, and architectural thinking skills
• Strong communication and cross-team collaboration abilities

Preferred Qualifications Experience designing complex coherent systems Deep knowledge of standards such as:

• CHI
• UCIe
• PCIe
• UAlink

Contributions to high-visibility industry NoC or SoC IP projects

Education Engineering degree, Master's, or PhD in electronics, computer engineering, or a related field, or equivalent professional experience.